Name : Dr.M.KANNAN

Designation : Professor 

Educational Qualification : Ph.D

Area of Specialization : VLSI  & Networking

Email ID : This email address is being protected from spambots. You need JavaScript enabled to view it.  

 IRINS Profile

• Educational Qualifications

   

   

  Sl.No.	Examination Passed	Name of the University/Board	Year of Passing/ awarded	Subject/ Specialization
  1)	PhD	Anna University, Anna University	(2001 - 2008)	Digital VLSI, Computer Architecture, Computer Networks
  2)	M.Tech.	Anna University	(1993 - 1995)	ELECTRONICS AND COMMUNICATION ENGG
  3)	B.E.	ACCET, Karaikudi, Madurai Kamaraj University	(1985 - 1989)	ELECTRONICS AND COMMUNICATION ENGG

   

   

   

   

   

   

   

   

   

   

• Post Held

   

  Post held	Period of Service		Name & Address of Employer
  	From	To
  Professor	26-July-2013	Till date	Dept of Electronics Engineering, MIT, Anna University, Chennai
  Associate professor	July-2009	25-July-2013	Dept of Electronics Engineering, MIT, Anna University, Chennai
  Assistant Professor	November-2008	July-2009	Dept of Electronics Engineering, MIT, Anna University, Chennai
  Lecturer Sl. Grade	July-2006	November-2008	Dept of Electronics Engineering, MIT, Anna University, Chennai
  Lecturer Sr. Grade	July-2001	July-2006	Dept of Electronics Engineering, MIT, Anna University, Chennai
  Lecturer	July-1996	July-2001	Dept of Electronics Engineering, MIT, Anna University, Chennai
  Teaching Fellow	August-1993	July-1996	Dept of Electronics Engineering, MIT, Anna University, Chennai

   

• Journals

   

  10. M. Kanmani, M.Kannan, " Blind channel estimation for Multiple Input and Multiple Output system using constant Modulus Algorithm", Computers and Electrical Engineering, published by Elsevier. (2015).

  9. Jessintha.D, Kannan.M, Srinivasan.P.L, "Energy Efficient VLSI Bassed DCT Architecture with Accurate Error Compensation", Applied Mechanics and Materials, published by Trans Tech Publications, Switzerland. Vol. 626, pp. 127-135 (2014).

  8. E.Konguvel, J.Raja, M.Kannan, " A Low power VLSI Implementation of 2 x 2 MIMO OFDM Transceiver with ICI-SC ", International Journal of Computer Applications, Vol. 77, Issue 5, (2013).

  7. V. Thirunavukkarasu and Dr.M Kannan, "Throughput, End-to-End delay and Utilization Analysis of Beacon Enabled and Non-Beacon Enabled WSN", European Journal of Scientific Research, pp. 196-209 (2012).

  6. V. Thirunavukkarasu and Dr.M Kannan, "Load Density Analysis of Beacon Enabled and Non - Beacon Enabled Wireless sensor Networks", European Journal of Scientific Research, pp. 135-145 (2012).

  5. J.Raja and M Kannan, "VLSI Implementation of High Throughput MIMO OFDM Transceiver for 4th Generation Systems", Indian Journal of Engineering and Material Science, pp. 307-319 (2012).

  4. V.Thirunavukkarasu, M.Kannan and S.R.Ramyah, "Load Density Analysis of Mobile Coordinator in a Hexagonal Configuration", European Journal of Scientific Research , Vol. 66, Issue 1, pp. 96-104 (2011).

  3. Sohil Shah, Preethi Venkatesan, Deepa Sundar, and Kannan.M, "Low Latency, High Throughput, and Less Complex VLSI Architecture for 2D-DFT", IAJIT, Vol.3

  2. M.Kannan, T.Aruna, S.K.Srivasa, "Hardware Implementation of Low Power High Speed FFT", IAJIT, Vol. 5, Issue 4, (2008).

   1. M.Kannan, S.K.Srivatsa, "Hardware Implementation of Instruction Level Parallel Architecture Incorporating special Function Units for Image Processing Algorithms", Information Technology, Issue 3, pp. 416-421 (2006).

• Conferences

  17. Sarathal, Kanmani.M, Kannan.M, "Performance Analysis of Co-operative MIMO Employing path and Antenna Selection" presented in a International level conference on Current Research in Engineering Science and Technology(ICCREST-2016), organised by Jayaram College of Engineering and Technology, India from 04-May-2016.

  16. Debasish Chakraborty, Kannan.M, "MIMO Signal Detection Based on Tree-Search involving Nodes at Multiple Depths and a Level Biased Metric Using Soft Decoding" presented in a International level conference on IEEE Internation Conference on Green Computing, Communication and Electrical Engg (ICGCCEE'14), organised by Dr. NGP Institute of Technology, India from 07-Mar-2014 to 08-Mar-2014.

  15. "MIMO Signal Detection Based on Tree-Search involving Nodes at Multiple Depths and a Level Biased Metric Using Soft " presented in a International level conference on IEEE Internation Conference on Green Computing, Communication and Electrical Engg (ICGCCEE'14), organised by Dr. NGP Institute of Technology, India from 07-Mar-2014 to 08-Mar-2014.

  14. Janakiraman, Kannan.M, "FPGA based Symbol Time and Frequency offset Estimation for Wireless OFDM System." presented in a International level conference on International Conferences on Advances in Science and Technology (ICAST-2014), Thailand from 14-Feb-2014 to 15-Feb-2014.

  13. on Empowering ASIC Front End to Meet the Challenges in the Ultra Deep sub- Micrometer, organised by MIT, India from 22-Feb-2007 to 24-Feb-2007.

  12. "Efficient FPGA implementation of I2C Bidirectional Serial Bus Controller" presented in a International level conference on NCVD-06, organised by PSG College of Engineering, Coimbatore, India from 03-Mar-2006 to 04-Mar-2006.

  11. "Efficient Hardware Implementation of LDPC Encoder in ASIC" presented in a National level conference on NCVD-06, organised by PSG College of Engineering, Coimbatore, India from 03-Mar-2006 to 04-Mar-2006.

  10. "Simulation Analysis of Re-engineered Legacy Engine Management System" presented in a International level conference on IP-SOC 2005, IP based SoC Design Conference & Exhibition, organised by IP-SOC 2005, IP based SoC Design Conference & Exhibition held at Grenoble, France, France from 08-Dec-2005 to 09-Dec-2005.

  9. "Simulation Analysis of Re-engineered Legacy Engine Management System" presented in a International level conference on IP- SOC 2005, France from 07-Dec-2005 to 08-Dec-2005.

  8. "Simulation Analysis of a low power Synchronous Token ring Based VLIW processor under GALS multiprocessor Technology with improved efficiency - Asynchronous FIFO Methodology" presented in a International level conference on 3rd International Computers, Communication and Control Technologies (CCCT '05), USA from 26-Jul-2005 to 30-Jul-2005.

  7. "Simulation Analysis of a low power Synchronous Token ring Based VLIW processor under GALS multiprocessor Technology with improved efficiency" presented in a International level conference on 3rd International Computers Design Conference (CDES'05), USA from 24-Jun-2005 to 27-Jun-2005.

  6.B.Vinayagasundaram, M.Kannan, S.K.Srivatsa, "Software Architecture quality in Artificial Intelligent Systems" presented in a International level conference on ICET 2004, organised by KIIT Bhuvaneswar, India from 24-Dec-2004 to 26-Dec-2004.

  . 5. P Prakash M Kannan, "Single Tree Search Sphere Decoding Algorithm for MIMO Communication System" presented in a National level conference on Single Tree Search Sphere Decoding Algorithm for MIMO Communication System, organised by Sri Sairam Engg College, India .

  4. Kaushik, Anusha.R, Surya Kumar.K, Kannan.M, "Empowering ASIC Front end to meet the challenges of the Ultra Deep Submicrometer" presented in a International level conference on IEEE-ICSCN2007, organised by MIT Campus, India.

  3. "Analysis and Implementation of Parallel Low Complexity Motion Estimation" presented in a International level conference on IEEE-ICSCN2007, organised by MIT Campus, India .

  2. "VLSI Implementation of Enhanced Successive Elimination Algorithm for Multimedia Processor" presented in a International level conference on ICSIP2006, India .

  1. "VLSI Implementation of Low Power High Throughput Low Density Parity Check Code Decoder for Optical Communication" presented in a International level conference on IEEE INDICON2006, New Delhi, India .

• Experience Abroad

   

  1. Visited University of Kaiserslautern, Kaiserslautern, Germany from 23-Mar-1998 to 08-May-1998. Purpose of visit :Training Programme- EMACs & System administrator.

• Invited Lectures

  6. Delivered a Lecture on "Recent Trends in VLSI Design" in Faculty Development Programme organized by Adhiparasalthi Engineering College, Melmaruvathur (05-Dec-2014).

  5. Delivered a Lecture on "Research Issues in VLSI Design and Testing" in Faculty Development Programme (TEQIP) organized by Government College of Engineering, Bargur, Bargur (20-Aug-2013).

  4. Delivered a Lecture on "Low Power Techniques in VLSI Design" in International Conference organized by SRM University, Kattankalathur, Chennai (14-Feb-2013).

  3. Delivered a Lecture on "VLSI Challenges" in International Conference organized by Syed Ammal Engineering College, Ramanathapuram (21-Sep-2012).

  2. Delivered a Lecture on "Digital Image Processing " in Digital Image Processing for Scientist(CEERI)CSIR organized by MIT Campus, Anna University, MIT Campus, Anna University (23-Nov-1999).

  1. Delivered a Lecture on "Windows -95 Operating System" in Intensive Computer Training Program for BC/MBC candidates organized by MIT Campus, Anna University, MIT Campus, Anna University (03-May-1999).

• Current Sponsored Projects

   1. "DRS-SAP Phase - II Project" ( April-2015). Project Cost: 1.48.

• Sponsored Projects Completed

  1. "Multimedia based process Automation over Internet using real time image processing. (1999-2003) Amount Rs. 25.77 Lakhs. Sponsored by the Ministry of", funded by DST, MInistry of Information and Technology (July-1999). Project Cost: 25.77L.

  2. "Design and Implementation of Foot Scanning System Amount Rs. 3.25 Lakhs. Sponsored by . Principal Investigator.", funded by CLRI Adayar (May-2000 - March-2002). Project Cost: 3.25L.

  3. "Design and Development of Electronic Dash Board" (July-1998.. Project Cost: 1.25L.

  4. "Study of Ericcson Switch Architecture" (July-2007 - December-2007). Project Cost: 8.00.

• Programme Organised

   

  19. Co-ordinator, National level workshop on "Embedded SOC Design" from 07-Mar-2016 to 08-Mar-2016.

  18. Co-ordinator, National level workshop on "Hands on training in Embedded C Programming of PIC Microcontrollers" from 01-Mar-2016 to 02-Mar-2016.

  17. Organiser/Co-ordinator, National level workshop on "Advancements in Bio Medical signal and Image Processing" from 29-Oct-2015 to 30-Oct-2015.

  16. Convener, International level workshop on "International Workshop on Network on Network Security & Challenges" from 17-Aug-2015 to 18-Aug-2015.

  15. Co -ordinator, National level Short Course on "FDP on Microprocessor and Microcontroller " from 08-Jun-2015 to 14-Jun-2015.

  14. Convener, International level conference on "ICSCN2015" from 26-Feb-2015 to 28-Feb-2015.

  13. Organiser/Co-ordinator, National level workshop on "Image Processing Framework using FPGA" from 15-Oct-2012 to 16-Oct-2012.

  12. Co-ordinator, National level workshop on "Embedded System Design using FPGA and ARM" from 04-Aug-2012 to 05-Aug-2012.

  11. Co-ordinator, National level workshop on "VLSI for Signal Processing" from 14-Mar-2011 to 15-Mar-2011

  10. coordinator, National level workshop on "Digital and Cellular Standards and their measurements " from 30-Apr-2010.

  9. C0-ordinator, National level workshop on "Development of Embedded Systems using C for ARM with Extensive Hands on Experience" from 07-Jan-2010 to 08-Jan-2010.

  8. Co-coordinator, National level workshop on "High Speed Digital Design" from 23-Oct-2009 to 24-Oct-2009.

  7. Co-ordinator, National level workshop on "Embedded Systems Design in FPGAs" from 07-Jan-2008 to 08-Jan-2008.

  6. Co-Coordinator, National level workshop on "Next Generation Wireless Networks" from 19-Sep-2007 to 20-Sep-2006

  5. Co-ordinator, National level workshop on "PC assembly, Servicing and Maintenance" from 01-Mar-2007 to 02-Mar-2007.

  4. Co-ordinator, National level workshop on "Custome IC Design Flow with Cadence Tools" from 22-Oct-2005.

  3. Co-ordinator, National level workshop on "Physical Design and Verification Issues in ASIC Design" from 09-Sep-2005 to 10-Sep-2005.

  2. Co-ordinator, National level workshop on "A Refresher Course onVLSI Design" from 28-Mar-2005 to 29-Mar-2005.

  1. Co-coordinator, National level Short Course on "Computer Networking for CVRDE " from 23-Dec-2002 to 27-Dec-2002.

• Programme Attended

  12. Attended a National level Short Course on "Robotics Technology for Manufacturing" organized by MIT Campus, Anna University, India from 10-Dec-2011 to 23-Dec-2011.

  11. Participated in a National level workshop on "ISTE Worshop on Basic Electronics" organized by IIT, Bombay, India from 28-Jun-2011 to 08-Jul-2011.

  10. Attended a International level Short Course on "Optimization Techniques in Power System Problems" organized by Adhiparasakthi Engineering College, Melmaruvathur, India from 01-Jun-2011 to 15-Jun-2011.

  9. Attended a National level Short Course on "Research Methodology" organized by Sona College of Technology, India from 18-Apr-2011 to 30-Apr-2011.

  8. Participated in a National level workshop on "Fusion of VLSI and Image Processing" organized by SKR Engineering College, India from 01-Dec-2010 to 04-Dec-2010.

  7. Participated in a National level workshop on "Pervasive and Ubiquitous Computing" organized by MIT Campus, Anna University, India from 03-Apr-2009 to 04-Apr-2009.

  6. Attended a National level Short Course on "Recent Advances in Unmanned Air Vehicles 2008" organized by MIT Campus, Anna University, India from 22-Sep-2008 to 25-Sep-2008.

  5. Participated in a International level workshop on "VLSI and Embedded System Tool" organized by ECE, CEG, AU, India from 25-Jan-2005.

  4. Attended a International level Short Course on "Mechatronics" organized by PT, MIT, India from 22-Nov-2004 to 11-Dec-2004.

  3. Attended a National level Short Course on "Web Services and Applications development Using C# and .Net frame work" organized by MIT, India from 10-Nov-2003 to 24-Nov-2003.

  2. Attended a National level Short Course on "Digital Image Processing and Geographic Information Systems" organized by IIT, Bombay, India from 14-Jun-1999 to 18-Jun-1999. 

  1. Attended a National level Short Course on "Multimedia Communication" organized by IIT, Madras, India from 24-Nov-1998 to 04-Dec-1998.

• Programme Chaired

   2. Chairman, International level conference titled "Recent Trends in Information Technology" conducted by MIT Campus, Anna University from 10-Apr-2014 to 12-Apr-2014.

  1. Chairman, International level conference titled "Internation Conference on VLSI and Embedded System" conducted by SRM University from 14-Feb-2013.

• Research Guidance

  Scholars On-Roll
  S.No	Name of the Scholar	Reg.No	Ph.D./ M.S.	Full Time/ Part Time
  1	Jesintha. D	2924439726	Ph.D.	Part Time
  2	Mahaboob Basha. S	1014439701	Ph.D.	Part Time
  3	Prakash.P	1013439703	Ph.D.	Part Time
  4	Jeyacaleb.J	1014439734	Ph.D.	Part Time
  5	Kanmani.M	1023439743	Ph.D.	Part Time
  6	Janakiraman.V	1015439758	Ph.D.	Part Time
  7	Hariharan. I	1513439209	Ph.D.	Full Time
  8	Konguvel.E	1414439815	Ph.D.	Part Time
  9	Sridevi. C	1524439551	Ph.D.	Part Time

   

• Honours

  1. " Student Team Runner up - Faculty Mentor -Altera Design Contest" given by Altera from India (2007).

• Membership in Professional Organizations

  1. Institution of Engineers
  2. IEEE
  3. CSI 

• Additional Responsibilities

  1. Zonal Co-ordinator, Anna University, Chennai during August-2013 and July-2014.
  2. Deputy Director, Anna University, Chennai and June-2011.
  3. Deputy Controller of Examination, Controller of Examination-MIT, Anna University, Chennai.