Name                                               :  Dr.D.Meganathan

Designation                                       : Associate Professor

Educational Qualification                     : Ph.D

Area of Specialization                          : VLSI

Email ID                                             :  This email address is being protected from spambots. You need JavaScript enabled to view it.

IRINS Profile

• Educational qualifications

   

          

  Sl.No.	Examination Passed	Name of the University/Board	Year of Passing/ awarded	Subject/ Specialization
  1)	Post-Doc (By award)	KTH Royal Institute of Technology, Sweden	2011	VLSI/NOC Design
  2)	PhD	CEG, Anna University	2009	VLSI/Analog IC Design
  3)	ME	PSG tech, Bharathiar University	2003	Applied Electronics
  4)	AMIE	The Institution of Engineers (I)	1999	ELECTRICAL  AND ELECTRONICS ENGINEERING

• Post Held

   

  Post held	Period of Service		Name & Address of Employer
  	From	To
  Associate Professor	01-June-2015	Till Date	Anna University, Chennai
  Assistant Professor (Senior Scale)	10/07/2008	May-2015	Anna University, Chennai
  Lecturer	10/07/2003	09/07/2008	Anna University, Chennai
  Lecturer	10/03/2003	08/07/2003	Srikrishna Engineering College, Coimbatore

   

• Research Experience

   

  Post doctorate  in school of information and communication technology, 2010 – 2011 KTH Royal Institute of technology, Sweden.

   

  Title of the work: Concept and Design of Exhaustive-Parallel Search Algorithm to Support Quality-of-service in Network-on-Chip.

   

  Brief synopsis of Research: The work explores the concept and design of exhaustive-parallel search algorithm to support quality-of-service in Network-on-Chip. The exhaustive-parallel algorithm searches minimal path between source and destination in a wave-propagation manner. The algorithm is free from routing deadlock and live-lock. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The proposed router achieves the bandwidth of 1250Gb/s. The NoC fabric is designed for 8X8 mesh architecture and its performance is evaluated.

   

  Ph.D in faculty of information and communication Engineering, 2004-2009, College of Engineering, Anna University, India.

   

  Thesis Title: A Power Optimized 10-bit 100MS/s Pipelined Analog-to-Digital Converter for High Speed Interface Circuits.

   

  Brief synopsis of Research: High-speed and medium-resolution Analog-to-Digital Converters (ADC) are widely used in commercial applications including data communication and image signal processing. In such applications, the reduction of power consumption associated with high speed sampling and high linearity is one key design issue in enhancing the portability and battery operation. Among many ADC architectures, pipelined ADC is proved to be the most suitable for high-speed, medium-resolution and low-power consumption. Advancement in fabrication technology reduces the feature size of the transistor and scales down the supply voltage. To achieve high linearity, high dynamic range and high sampling speed simultaneously under low supply voltages in deep submicron Complementary Metal Oxide Semiconductor (CMOS) technology with low power consumption has been considered as extremely challenging. Thus, the objective of this work is to design and implement a low-voltage, low-power, medium-resolution and high-speed pipelined ADC in deep submicron CMOS technology.

   

  Masters in Department of Electrical and Electronics Engineering,2001-2003, PSG College of Engineering and Technology, India

   

  Project Title: Design and control of BLDC Motor using Microcontroller for Two Wheelers.

    

  Brief synopsis of project: The main objective of the project is to Design and develop a Brushless D.C Motor (BLDC) with control circuit for the operation of the hybrid electric vehicle (HEV) to be used in a two wheeler. The hybrid electric vehicle combines the power and the range of the conventional internal combustion (IC) vehicle with the zero-emission advantage of an electric vehicle creating an automotive solution for the polluted Indian roads. A HEV runs as a battery electric vehicle at the time of starting and runs up to 20 km per hour speed, beyond that it switch over to IC engine. The motor was fitted with the controller circuit in an existing two-wheeler and the performance was studied. The above project was carried out in M/s LUCAS-TVS, Chennai, India. 

• Work Experience

   

  2010 – 2011 Visiting Researcher, School of ICT , KTH Royal Institute of Technology, Sweden 

   

  I worked as a part of Professor Axel Jantsch research group in the field of network-on-chip. My research work involved in design and implementation of high performance interconnects to support quality of transmission in NoCs. I have developed a concept of exhaustive-parallel search algorithm which guarantees quality of transmission and setup latency. 

   

  2003 - till date Assistant Professor, Department of Electronics Engineering, Madras Institute of Technology, Anna University, India 

   

  I work as a regular faculty member in the department of electronics engineering. I have passion to teach electronics and VLSI related subjects. Besides teaching I have guided four numbers of post-graduate research projects and thirty numbers of undergraduate research projects. I worked as mentor for Texas-Instruments and IBM student projects. I have delivered several guest lectures on analog-integrated circuit design, VLSI Design, Electronic Circuits in various colleges/universities across India. 

   

• Fellowship

  EURINDIA Fellowship (2010-2011) to pursue post-doctorate research in KTH Royal Institute of technology, Sweden. 

• Journals

   

  1. D. Meganathan, S. Moorthi, Amrith Sukumaran, M. M. Dinesh Babu and J. Raja Paul Perinbam, “A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter”, Journal of Low Power Electronics Vol.4, 1–20, 2008.
  2. Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P. and Raja Paul Perinbam J., Low Jitter ADPLL based Clock Generator for High Speed SoC Applications’,         International Journal of  Electrical Computer and Systems Engineering, IJECSE Vol. 96, No. 11,  1183–1189,2009.
  3. D. Meganathan, A. Sukumaran, M.M.DineshBabu, S.Moorthi, Deepalakshmi R, “A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC” International Journal of  Microelectronics Journal Volume 40, Issue 10, pp.1417-1435, 2009.                                           
  4. D. Meganathan, Raja Paul Perinbam, R.Deepalakshmi, “High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC”, International Journal of High Performance Systems Architecture, Vol. 2, No. 1, 2009.
  5. D.Meganathan, “A 24.5mW, 10-bit, 50MS/sec CMOS pipelined Analog-to-Digital Converter” International Journal of High Performance Systems Architecture, Vol. 3, No. 4, pp-184-200, 2011.
  6. Jose Anand, J. Raja Paul Perinbam, and D. Meganathan, " Performance of Optimized Routing in Biomedical Wireless Sensor Networks using Evolutionary Algorithms", Comptes rendus ’Academie bulgare des Sciences, published by ENGINEERING SCIENCES. Vol. 68, Issue 8, pp. 1049-1054 (2015).
  7. Umamaheswari S , Meganathan D and Raja Paul Perinbam J, " Runtime Buffer ManagementTo Improve The Performance In Irregular Network-on-Chip Architecture", Journal of Systems Architecture, published by Sadhana, Indian Academy of Sciences, Springer. Vol. 10, Issue 4, pp. 1117-1137 (2015). 
  8. Jose Anand, J. Raja Paul Perinbam, and D. Meganathan, " Design of GA-Based Routing In Biomedical Wireless Sensor Networks", International Journal of Applied Engineering Research , Vol. 10, Issue 4, pp. 9281-9292 (2015).
  9. Jose Anand, J. Raja Paul Perinbam, and D. Meganathan, " PSO based Optimized Routing in Biomedical Wireless Sensor Networks", Jokull Journal, Vol. 65, Issue 3, pp. 9281-9292 (2015).
  10. D.R. Denslin Brabin, Raja Paul Perinbam, and D. Meganathan, " A High Capacity Data Hiding Scheme for Digital Images Using Normalization", International Journal of Applied Engineering Research, Vol. 10, Issue 1, pp. 1341-1350 (2015).
  11. Roy Francis, Meganathan D, "An Improved ANFIS with Aid of ALO Technique for THD Minimization of Multilevel Inverters", Journal of Circuits, Systems and Computers, , published by World Scientific. Vol. 27, Issue 12, (2018).
  12. Roy Francis, Meganathan D, " A Novel DDS Architecture for Dynamic Reconfigurable Three Phase Induction Motor Drive,", Journal of Electrical Engineering, published by University . Vol. 18, Issue 2, pp. 1-7 (2018).
  13. Madhusudhana Reddy Barusu, Umamaheswari Sethurajan, Meganathan Deivasigamani, " A non-invasive method for rotor bar fault diagnosis in three-phase squirrel cage induction motor with advanced signal processing technique", Journal of Engineering, published by IET. pp. 1-6 (2018).
  14. Madhusudhana Reddy Barusu, Umamaheswari Sethurajan, Meganathan Deivasigamani,"Low-cost SPLL-based electrical faults identification for three-phase squirrel cage induction motor using handheld Doppler radar signal analysisMadhusudhana Reddy Barusu", IET Power Electronics, published by IEEE. Vol. 11, Issue 7, pp. 1205-1216 (2018).
  15. Madhusudhana Reddy Barusu, Umamaheswari Sethurajan, Meganathan Deivasigamani, "Diagnosis of Bearing Outer Race Faults Using a low-cost non-contact method with Advanced Wavelet Transforms", Elektronika ir Elektrotechnika, published by ELEKTRONIKA IR ELEKTROTECHNIKA. Vol. 25, Issue 1, pp. 44-53 (2019).
  16. S.Balaji, D.Meganathan, "FPGA accelerated computing for particle identification in high-energy physics  experiments", IOP Press, published by IOP Press. pp. 1-6 (2019).
  17.  Roy Francis and D.Meganathan, "A dual-mode cascaded H-bridge multilevel inverter for improving THD", Journal of Electrical Engineering,, published by Springer. Vol. 101, Issue 1,pp. 225-236 (2019).
  18. S.Balaji, D.Meganathan and S.Ramasamy, "Single-Event-Hardened Timing Generator for waveform digitizer based readout electronics", Journal of Instrumentation , published by IOP Press. Vol. 14, pp. 1-8 (2019).
  19.  S.Jagannathanan, V. Sathiesh Kumara and D. Meganathan, " Design and Implementation of In-situ Human-Elephant Conflict Management", of Intelligent and Fuzzy Systems, , published by IOS Press. Vol. 36, Issue 3, pp. 2005-2013 (2019).
  20. D.R.Denslin Brabin, J.Rajapaul Perinbam, D.Meganathan, "Watermark visibility adjustable RVW scheme for JPEG images", Wireless Personal Communication, published by Springer.(2020).
  21.  K.Pandiammal, D.Meganathan, "Efficient design of QCA based hybrid multiplier using clockzone based crossover", Analog Integrated Circuits and Signal Processing, Vol. 102, pp. 63-77(2020). 
  22.  Madhusudhana Reddy Barusu, D. Meganathan, " Non-invasive Vibration Measurement for Diagnosis of Bearing Faults in 3-Phase Squirrel Cage Induction Motor Using Microwave Sensor", IEEE Sensors, published by IEEE. Vol. 21, Issue 2, pp. 1026-1039 (2021).
  23. Jagadeeshkumar N & Meganathan D, " A systematic design of novel energy efficient 64-bit parallel-prefix adder", International Journal of Electronics, published by Taylor and Francis. pp. 1-22 (2021).
  24. R. Denslin Brabin, J. Raja Paul Perinbam, D. Meganathan,, "A Block Based Reversible Data Hiding Scheme for Digital Images Using Optimal Value Computation", Wireless personal communication, published by Springer. Vol. 94, Issue 10, pp. 1-14 (2016).

  National Journal

  1. Jose Anand, J. Raja Paul Perinbam & D. Meganathan, "Q-Learning-Based Optimized Routing in Biomedical Wireless Sensor Networks", Networks’ IETE Journal of Research, published by Taylor and Francis . Vol. 63, Issue 1, pp. 89-97 (2017). 

• Conferences

  International Conferences

  1. Madhusudhana Reddy Barusu. Umamaheswari Sethurajan, Meganathan D, "A non-invasivemethod for rotor bar fault diagnosis in three-phase squirrel cage induction motor with advancedsignal processing technique" presented in a International level conference on The 9thInternational Conference on Power Electronics, Machines and Drives, organised by IET,Liverpool, UK from 17-Apr-2018 to 19-Apr-2018.
  2. Madhusudhana Reddy Barusu. Umamaheswari Sethurajan, Meganathan D, "Diagnosis ofBearing Outer Race Faults Using a low-cost non-contact method with Advanced WaveletTransforms" presented in a International level conference on ELECTRONICS -2018Conference, Lithuania, UK from 18-Jun-2018 to 20-Jun-2018.
  3. S.Jagannathan, V.Sathiesh Kumar and D.Meganahan, "Design and Implementation of In-situHuman-Elephant Conflict Management System" presented in a International level conferenceon Fourth International Symposium on Intelligent Systems Technologies and Applications ,organised by ISTA’18, India from 19-Sep-2018 to 22-Sep-2018.
  4. Pandiammal.K and D.Meganathan, "Design of 8 bit Reconfigurable ALU Using Quantum DotCellular Automata" presented in a International level conference on IEEE 13th Nanotechnology Materials and Devices Conference (NMDC), USA from 14-Oct-2018 to 17-Oct-2018.
  5. Jagadeesh Kumar N and Meganathan D, " A Novel Design of Low power and High speed Hybrid Multiplier " presented in a International level conferenceon 4th International Conference on Signal Processing, Communications and Networking,organised by Department of Electronics Engineering, MIT Campus, Anna University, India from16-Mar-2017 to 18-Mar-2017.
  6. Pandiammal K and Meganathan D, "QCA Based FIR Serial Multiplier using cut-set algorithm"presented in a International level conference on IEEE-Nano-2017, organised by Department ofElectrical and Computer Engineering, University of Pittsburgh, USA from 25-Jul-2017 to28-Jul-2017.
  7. S.Saranya, G.Sumithra, D.Meganathan, "An Approach to detect dolphin whistle from underwater sounds" presented in a International level conference on 3rd International Conference on Trends in Technology and Engineering, organised by ARJUN COLLEGE OF TECHNOLOGY, INDIA from 20-Apr-2016 to 20-Apr-2016.
  8. G.Sumithra, D.Meganathan, M.K.Suresh, "Noise Reduction in Underwater Acoustic Signals for Tropical and Subtropical Coastal Waters" presented in a International level conference on IEEE / OES, CHINA OCEAN ACOUSTICS SYMPOSIUM, COA 2016, organised by HARBIN ENGINEERING UNIVERSITY, CHINA &UNIVERSITÉ LIBRE DE BRUXELLES, BELGIUM, CHINA from 09-Jan-2016 to 11-Jan-2016.
  9. G.Sumithra,P.Yogapriya,D.Meganathan, "Shallow Water Path Model For Underwater Acoustic Communication" presented in a International level conference on 3rd International Conference and Exhibition on Underwater Acoustics, organised by FOUNDATION FOR RESEARCH &TECHNOLOGY HELLAS ; IACM – INSTITUTE OF APPLIED &COMPUTATIONAL MATHEMATICS , Greece from 21-Jun-2015 to 26-Jun-2015.
  10. Roy Francis, Meganathan. D, “Novel Static Reconfigurable PWM controller for Three Phase Induction motor drive”, Proceedings of the 8th International Conference on Science, Engineering and Technology (SET-2014),May 2014.
  11. Umamaheswari S , Meganathan D and Raja Paul Perinbam “Customized Adaptive Algorithm for Deadlock Free routing in irregular mesh NoC”, Proceedings of IET, 4th International Conference on Sustainable Energy and Intelligent system” Dec-12-14,2013.
  12. D.Meganathan, Shaghayeghsadat Tabatabaei, Axel Jantsch, Naveed Mustafa, Hamza Ijaz, Haris Bin Aslam, Shaoteng Liu, “Concept and Design of Exhaustive-Parallel search algorithm to support Quality-of-service in Network-on-Chip”, IEEE proceedings of SoCC-2011Conference,pp.150-155.
  13. D. Meganathan, Axel Jantsch, “A low-power, medium-resolution and high-speed CMOS pipelined ADC”, IEEE Proceedings of Norchip 2010 conference, pp-1-4.
  14. S.Moorthi, Meganathan D, J Raja Paul Perinbam,(2008) ‘A Low jitter ADPLL based clock generator circuit for High speed SoC applications’ in International conference on Computer Electrical and Systems Science and Engineering, Vol.33.

  National Conferences

  1. Meganathan D., Vishnu K.G., Hariharan and Raja Paul Perinbam J. (2007), ‘Macro-level Model of Pipelined ADC’, Proceedings of the International Conference on Modelling and Simulation, CITCOM 07,Coimbatore, India, Aug 27-29, Vol. 3, pp. 115-119. 
  2. Avijith singh, Meganathan D. and Raja Paul Perinbam J. (2008), ‘A Sub 1V low Power Voltage Reference Generator’, Proceedings of two day National Conference on Signals Systems and Communication, NCSSN’08, Chennai, India, May 8-9, pp. 184-187.
  3. K.Bhulakshmi, Meganathan D,(2008) ‘VLSI Implementation of Enhanced Encryption Techniques for public protocols’ Published in 4th National Conference on Signals, Systems and Communication.
  4. V. Ramana, Meganathan D.(2006) ‘Improving test effectiveness of SCAN based BIST by scan chain partitioning’ Published 2nd National Conference on Signals, Systems and Communication.

• Books authored

  1. D.Meganathan, “Hand-Book on Marine Electro technology for Marine Engineers” Chennai School of Ship Management, 2000.
  2. "Electronic Circuits-I" authored by D.Meganathan and published by Yesdee, Chennai.(2021)

• Programme Organised

   

  Sl.No.	Name of the Course	Duration	Venue
  1	Coordinator, National level workshop on "Advanced Digital Design Flow using CADENCE"	01-Mar-2018 to 03-Mar-2018	-
  2	Active member, International level conference on "4th International Conference on Signal Processing, Communications and Networking"	16-Mar-2017 to 17-Mar-2017.	-
  3	Workshop Coordinator, National level Short Course on "CMOS, Mixed Signal and Radio Frequency VLSI Design"	30-Jan-2017 to 04-Feb-2017.	-
  4	Coordinator, International level workshop on "UGC sponsored workshop on Embedded SoC Design"	07-Mar-2016 to 08-Mar-2016.	-
  5	Working Committee Member, International level conference on "3rd International conferenceon “Signal Processing, Communication and Networking (ICSCN 2015)"	26-Mar-2015 to28-Mar-2015.	-
  6	Two days workshop on Digital and Custom IC Design using CADENCE	Oct-17 & 18, 2014	Department of Electronics Engineering, MIT,AU
  7	Hands on training on VLSI System Design (RTL-GDSII) using CADENCE	Sep-22, 2014	Department of Electronics Engineering, MIT,AU
  8	Hands on training on Embedded System Design using ARM Controller	Sep-2,2014	Department of Electronics Engineering, MIT,AU
  9	One week Faculty development training program on VLSI Design	Dec 9-15,2013 (7-days)	Department of Electronics Engineering, MIT,AU
  10	Two-day Work-shop on Image processing frame work using FPGA”	Oct 15-16,2012 (2-days)	Department of Electronics Engineering, MIT,AU
  11	UGC Sponsored Two-day seminar on “Analog IC Design”	Sep 14-15,2012 (2-days)	Department of Electronics Engineering, MIT,AU
  12	Guest lecture on “Amplifier Design”	01-09-2009 (one-day)	Department of Electronics Engineering, MIT,AU
  13	Soft Skill Development Sponsored  by UGC for rural students	March-10 to 28, 2008	Department of Electronics Engineering, MIT,AU
  14	ASIC Design flow ( for Undergraduate and Post graduate students)	Sep 01-02, 2007 (02 days)	Department of Electronics Engineering, MIT,AU
  15	ARM Processor based development System (for Staffs and students)	May 23-24,2007 (02 days)	Department of Electronics Engineering, MIT,AU

   

• Invited Lectures Delivered

  Sl.No.	Topic of the lecture	Delivered on	Engineering College
  1	MOS Fabrication Techniques and CMOS Inverter	16-Nov-2018	Two week FDTP on VLSI Design-EC6601 organized by College of Engineering/Department of ECE, Chennai
  2	Hardwares in Networking"	16-Aug-2018	Guest Lecture organized by Valliammal  Engineering College/Department of Elect, Chennai
  3	Digital Circuit Design Digital Circuit Design" in Basic Concepts in Electronics andCommunication Lab Experiments	25-Jun-2018	Madras Institute of Technology/Department ofElect, Chenna
  4	CMOS Layout and Stick Diagrams	23-Nov-2017	Seven Days FDTP on VLSIDesign-EC6601 organized by Madras Institute of Technology/Center for Faculty , Chennai
  5	MOS Transistor Principles	20-Nov-2017	Seven Days FDTP on VLSIDesign-EC6601 organized by Madras Institute of Technology/Center for Faculty , Chennai.
  6	Electronic Circuits Design" in Basic Concepts in Electronics and Communication Lab Experiments	27-Jun-2017	Madras Institute of Technology/Department ofElect, Chennai .
  7	ADVANCED VLSI DESIGN TECHNIQUES	04-Aug-2016	VINAYAKA MISSIONS UNIVERSITY, Chennai .
  8	Challenges in Analog IC Design	14-Jul-2016	KCG College of Technology, Karapakkam, Chennai .
  9	Challenges in Analog IC design	19-Mar-2015	Conference organized by Anna University, Tirunelveli, Tirunelveli, Tamilnadu, India
  10	BJT Amplifiers	26th June 2014	Department of ECE, Dhanalakshmi College of Engineering, Tambaram, Chennai
  11	CMOS Inverter design	10th Dec 2013	Department of Electronics Engineering, MIT, AU.
  12	Analog VLSI Design	26th July 2013	Department of ECE, Anna University, Chennai-25.
  13	Challenges in Analog IC Design	14th Sep 2012	Department of Electronics Engineering, MIT Campus, Anna University,
  14	Guest lecture on Feedback Amplifiers	03/02/2010	VEL-Tech Multitech Engineering College Chennai
  15	Feedback Amplifiers	30.09.2009	RMK Engineering College, Chennai
  16	Introduction to Analog VLSI	01.09.2008	Vellore Institute of Technology University, Vellore.
  17	Analog Integrated circuit design	Dec 03-05, 2008	Lourdes Matha College of Science and Technology, Kerala

• Programme Attended

   

   

  Sl.No.	Title	Venue	Duration	Sponsoring Authority
  1	National level Short Course on "Personality Development and NLP".	National Institute of Technical Training & Research, India	20-Aug-2018 to 25-Aug-2018	National Institute of Technical Training & Research, India
  2	National level Short Course on "Professional Ethics and Values".	NITTTR, Chennai, India	27-Nov-2017 to 01-Dec-2017.	NITTTR, Chennai, India
  3	National level workshop on "High Frequency Design using ADS"	Department of Electronics Engineering, MIT Campus, Anna University, India	11-Aug-2017to 11-Aug-2017	Department of Electronics Engineering, MIT Campus, Anna University, India
  4	National level Short Course on "One Week ISTE STTP for Coordinators on CMOS,Mixed Signal and Radio Frequency VLSI Design"	IIT-Kharagpur, India	19-Sep-2016 to 23-Sep-2016	IIT-Kharagpur, India
  5	National level workshop on "Two Days workshop on Advancement in Biomedical Signal and Image Processing".	MIT Campus, India	29-Oct-2015to 30-Oct-2015	MIT Campus, India
  6	Participated in a International level workshop on "Hands-on Digital Signal Processing"	ARM University Program, , Hyderabad, India	20-Aug-2015 to 21-May-2015	ARM University Program, , Hyderabad, India
  7	Attended a National level Short Course on "FDP on Microprocessor and Microcontroller"	Madras Institute of Technology, Anna University, India	08-Jun-2015 to 14-Jun-2015	Madras Institute of Technology, Anna University, India
  8	One week Faculty development training program on VLSI Design	MIT Campus	Dec 9-15,2013 (7-days)	AICTE
  9	CMOS VLSI Design	NIT Calicut	23-29  June 2013 (7 days)	AICTE
  10	Robotics Technology for Manufacturing	MIT Campus	10/12/2011 to 23/12/2011 (14-days)	AICTE
  11	FDP on Digital Signal Processing	MIT Campus	28/11/2011 to 04/12/2011 (7 days)	Centre for FDP,Anna University
  12	Advances in wireless Communication and networking Technologies	NIT-Calicut	13/06/2011 to 24/06/2011 (12 days)	MHRDE-AICTE
  13	Course on “Floorplanning, Physical synthesis, Place and Route (Flat and Hierarchical)+Low power implementation”	KTH-Royal Institute of Technology, Sweden.	20/09/2010 to 28/09/2010 (10 days)	KTH-Royal Institute of Technology
  14	One day workshop on Pattern recognition	MIT Campus	19/03/10 (one day)	MIT Campus
  15	TI Developer Conference	Leela Palace, Bangalore	29/07/2007 to 30/07/2007 (2 days)	Texas Instrument
  16	Two Weeks Course on Analog Design	TCE, Madurai	04/06/2007 to 15/06/2007 (12 days)	Texas Instrument
  17	One day workshop on Engineering trends in VLSI and ASIC design	CEG, Anna University	07/04/07 (one day)	Anna University
  18	Embedded Systems and Technology	IIT Kharagpur	19/06/2006 to 24/06/2006 (6 days)	TEQIP.
  19	Digital Signal Processing	CEG, Anna University	13/06/05 to 18/06/05 (6 days)	CEG, Anna University.
  20	VLSI and Embedded system Tool	CEG, Anna University	25/01/05 (one day)	CEG, Anna University.
  21	VLSI Design	CEG, Anna University	21/06/2004 to 27/06/2004 (7 days)	CEG, Anna University
  22	RE-Engineering teaching skills	MIT, Anna University	06/04/2004 to 07/04/2004 (2 days)	MIT, Anna University
  23	Digital Signal Processing	CEG,Anna University	18/11/2003 to 22/11/2003 (5 days)	CEG,Anna University
  24	Three days training program on “Modern teaching Competencies for faculty members	Sri Krishna College of Engineering and Technology	21/03/2003 to 23/03/2003 (3 days)	Sri Krishna College of Engineering and Technology

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

• Purchase Activity

   

   

   

  Sl.No.	Hardware/ Equipment purchase	Amount Approximately
  1)	MATLAB-Full Suite	Rs.15,00,000/-
  2)	Digital Storage Oscilloscope	Rs.4,00,000/-
  3)	Mixed Signal Oscilloscope	Rs.6,02,000/-
  4)	Function Generator	Rs.3,00,000/-
  5)	Red-had Linux Software for CADENCE platform	Rs.25,000/-
  5)	Rivera IPT	Rs.12,00,000/-
  6)	ARM Processor based Development Systems (Embedded Systems)	Rs.12,00,000/-
  7)	Logic Analyzer	Rs. 4,50,000/-
  8)	RFID, Sensor networks and Digital Storage Oscilloscope	Rs. 2,50,000/-
  9)	CADENCE Full Suite	Rs.14,00,000
  10)	Mixed Signal Oscilloscope (5)	Rs.9,00,000
  11)	Arbitrary Function Generator 40 MHz (5)	Rs.6,00,000
  12)	Digital Multimeter-5.5 digit (2)	Rs.1,00,000
  13)	Variable Power Supply (20)	Rs.5,00,000
  14)	3-MHz Function Generator (30)	Rs.3,00,000

   

• Student Activities

   

  i)                    President-EEA 

  I have been nominated as President, Electronic Engineer Association (EEA) in the Department of Electronics Engineering, MIT, AU for the academic year of 2013-14. EEA conducts various technical events like apocalypse, Electro focus etc., Besides our regular EEA activities, EEA organized several workshops, arranged GATE coaching and placement training for the students of the Department of Electronics Engineering, MIT Campus, Anna University during 2013-14. EEA awarded 10-scholarships for economically weaker students.

   

  ii)                  Coordinator- IETE Student Chapter  

  Organized invited lectures by eminent personalities from industries and academics. This chapter had largest strength among IETE student chapter of Tamilnadu.

   

  Sl.No.	Topic of the lecture	Delivered on	Expert Name and Address
  1)	Recent trends in Broad band Technologies	26.10.2006	Mr.A.Ganesan, Divisional General Manager, BSNL Chennai Circle- Chennai
  2)	Short term course on ASIC Design Flow	September 01-02,2007	1) Dr. J.Raja Paul Perinbam, Professor Anna University 2) Mr.S.Moorthi, Lecturer, NIT Trichy 3) Mr. A. Ganesan, Divisional General Manager, BSNL Chennai Circle- Chennai.

• Funded Projects

   

   

  S.No	Sponsored/ Consultancy Projects	Sponsoring Authority	Funds Sanctioned	Present Status
  1)	Design and Analysis of Phase locked loop based high speed clock generation for system on-chip applications	TEQIP-Networking	Rs.2Lacs	Completed
  2)	A Proposal for Low cost human-elephant conflict management in wildlife	Aeronautical Research & Development Board (Sigma Panel)	Rs 19,61,900 /-	Completed

   

   

• Ph.D Guidance(at present)

   

  Ph.D Completed
  Name of the PhD Scholar	Mode	Title of the Research work
  Mrs.S. Uma Maheswari	Part-time (Internal)	Performance Enhancement in NoC applications
  Mr.Roy Francis	Part-time (QIP)	Dynamic Reconfigurable Multilevel Inverter
  Mr. .Madhusudhana Reddy Barusu	Part-time (External)	Mutually Synchronized Oscillator’s Network for Clock Distribution on Large-Scale SOCs
  Ph.D On-Roll
  Name of the PhD Scholar	Mode	Title of the Research work
  Mr. N.Jagadeesh Kumar	Part-time (Internal)	Digital Logic Design using CNTFET
  Ms.K.Pandiammal	Part-time  (External)	Digital logic Design using Quantum-Cellular-Automata
  Ms. G. Sumithra	Part-time (Internal)	Under water Acoustic Communication

   *Welcoming young enthusiastic, dynamic minded people who want to pursue PhD

• Reviewer

   

  Reviewer for Elsevier Microelectronics Journal 

• Prizes,Awards Received

   

  (i) I have received prize award from the Institution of Engineers (I) for securing highest marks in aggregate amongst the successful candidates  in AMIE (Sec-B) Winter 1999 Exams.

  (ii) I have received IBM University relationship award for mentoring UG students,2011

   

• Subjects Handled

  UG Program

  1)      Electronic Circuits I

  2)      Electronic Circuits II

  3)      Digital System Design

  4)      Digital VLSI

  5)      Analog IC Design

  6)      Circuit Analysis

  7)      VLSI Design

  8)      Electron Devices

  9)      Electromagnetic Field theory

  10)  Network Analysis and Synthesis

  11)  Neural Networks and Fuzzy Logic Design

  PG Program

  1)      VLSI Design Techniques

  2)       ASIC Design

  Analog IC Design

• Additional Responsibilities

   

  1. Serving as Faculty Advisor since-2003.
  2. Guiding PG/UG Projects.
  3. Served as NRI Coordinator.
  4. Served as Part-time Coordinator.
  5. Handled Part-time classes continuously from 2003-2012.
  6. Actively involved in the syllabus framing work (2004,2008 & 2012).
  7. Developed Full-Fledged Analog VLSI Lab in the Department of Electronics Engineering, MIT Campus, Anna University.
  8. Served as Project Coordinator for PhD/PG/UG students.
  9. Guided Several PG and UG Projects.
  10. Working team member for International Conference on Signals, Communication and Networking Conferences -2007 and 2008.
  11. Executive Warden, Madras Institute of Technology, Anna University, Chennai from September-2019.
  12. Class Committee Chairman-(ME VLSI Design and Embed, Department of Electronics Engineering, Anna University, Chennai from June-2018.
  13. Class Committee Chairman -(be-i Year), Department of Electronics Engineering, Anna University, Chennai during December-2017 and May-2018.
  14. Faculty Advisor, Department of Electronics Engineering, Anna University, Chennai during August-2015 and July-2016.
  15. Class Committee Chairman (me-vlsi Design And Embed, Department of Electronics Engineering, Anna University, Chennai during July-2015 and December-2017.
  16. Deputy Warden, , Anna University, Chennai during August-2014 and September-2019.
  17. President Electronics Engineers Association, Department of Electronics Engineering, Anna University, Chennai during August-2013 and April-2014.
  18. Faculty Advisor, Department of Electronics Engineering, Anna University, Chennai during August-2011 and April-2015.
  19. Facutly Advisor, Department of Electronics Engineering, Anna University, Chennai during August-2007 and April-2010.
  20. Additional Chief Superintendent For End Semester E, MIT, Anna University, Chennai during Novem ber-2005 and January-2006.
  21. Additional Course Coordinator, Department of Electronics Engineering, Anna University, Chennai during August-2003 and April-2008.
  22. Faculty Advisor, Department of Electronics Engineering, Anna University, Chennai during July-2003 and April-2007.