Name : Dr.N.jagadeesh Kumar
Designation : Teaching Fellow
Educational Qualification : M.E., Ph.D
Area of Specialization : VLSI
Name of the University/Board
Year of Passing/
Madras Institute of Tech, Anna university, Anna University
(2009 - 2011)
ELECTRONICS AND COMMUNICATION ENGG
Govt. college of Engg, Krishnagiri, Anna University
(2003 - 2007)
ELECTRONICS AND COMMUNICATION ENGG
Period of Service
Name & Address of Employer
Department of Electronics Engineering, Madras Institute of Technology, Anna University, Chennai
- N.Jagadeeshkumar, K.Mariammal, “ Hilbert transform of wavelets using down sampling approach” National conference on Microwave and optical communication, NCMOC- 2011.
- P.Naveen kumar, N.Jagadeeshkumar, “Performance analysis of energy efficient carbon nano tube field effect transistor VLSI adder”, international conference on computer science and engineering, (ICCSE)april -2013
- N.jagadeesh kumar,D. Meganathan V.venkatesh P.namachivayam, "Design and analysis of CNTFET based SRAM in 32nm Technology" presented in a International level conference on Internationjal conferrence on advances in design and manufacturing, organised by Natational Institute of tecnology ,Trichy,Tamilnadu, india from 05-Dec-2014 to 12-Dec-2014
- Jagadeeshkumar.N,Meganathan .D, "A Novel Design of Low power and high speed hybrid Multiplier" presented in a International level conference on International conference on signal processing ,communication and Networking, 2017, organised by Anna University, india from 16-Mar-2017 to 18-Mar-2017
- L.rachel N.jagadeeshkumar “Design of truncated fixed width usigned baugh –wooly multiplier”. International conference on recent trends in science and technology (ICRTST) April 2018
- R.praveeen kumar N.Jagadeesh kumar High performance truncated Multiplier , international conference (ICRTST), April 2018
- K.Karthika N.jagadeeshkumar “Implemetation of modular multiplier in truncated multiplication”National conference on emerging trends in VLSI embedded &nano technologies National conference NCEVENT-2K18 April2018.
- Jagadeeshkumar N : Meganathan D, "A Novel Ultra-Low Power 6T/8T SRAM Design Using 9nm Heterojunction Tunnel Field-Effect Transistors", International Journal of Management, Technology And Engineering, pp. 3324-3331 (2019).
- Jagadeeshkumar N : Meganathan D, "Systamatic design of novel energy efficient 64 bit paralllel prefix adder", International journal of electronics ,Taylor & Francis (2021).
16. Participated in a National level workshop on "CMOS MIxed Signal and Radio frequency VLSI
15. Design" organized by IIT KHARAGPUR, INDIA from 30-Jan-2017 to 04-Feb-2017.
14. Participated in a National level workshop on "faculty development programme to “Enable
13. AICTE induction programme for students”" organized by ANNA UNIVERSITY, Tamilnadu from 18-Jun-2018 to 29-Jun-2018.
12. Participated in a International level workshop on "Design of algorithm" organized by National mission on Education Through ICT, india from 25-Mar-2016 to 30-May-2015.
11. Participated in a International level conference on " 3rd international Conference on signal processing.communication and networking(ICSCN 2015)" organized by Madras institute of technology chrompet chennai, india from 26-Mar-2015 to 28-Mar-2015.
10.Attended the faculty development program for VLSI design on 9th to 15th December 2013 in MIT chrompet
9.Attended the faculty development program training on design finishing for chip tapeout on 17-29th june 2013,RMK engg college ,Chennai.
8.Attended the workshop on Image processing Frame work using FPGA on 15-16th oct 2012 in MIT chrompet.
7. Attended a National level seminar on "ANALOG IC DESIGN" organized by MIT CHROMPET, INDIA from 14-Sep-2012 to 15-Sep-2012.
6. Participated in a National level workshop on "VIDEO ANALYTICS" organized by MIT,CHROMPET ,ANNAUNIVERSITY, INDIA from 28-Mar-2012 to 29-Mar-2012.
5. Participated in a National level workshop on "UGC SPONSORED WORKSHOP ON SOFT COMPUTING" organized by MIT,CHROMPET,ANNAUNIVERSITY, INDIA from 21-Mar-2012 to 22-Mar-2012.
4. Attended a National level seminar on "RESEARCH CHALLENGES IN WIRELESS SENSOR NETWORKS" organized by MIT, CHROMPET,ANNAUNIVERSITY, INDIA from 03-Mar-2010.
3. Participated in a National level workshop on "NEXT GENERATION WIRELESS TECHNOLOGIES-LONG TERM EVALUATION" organized by MIT ,CHROMPET, ANNA UNIVERSITY, INDIA from 04-Dec-2009 to 05-Dec-2009.
2. Participated in a National level workshop on "IMAGE PROCESSING FRAMEWORK USING FPGA" organized by MIT,CHROMPET,ANNAUNIVERSITY, INDIA.
1. Participated in a International level workshop on "Design of algorithm" organized by National mission on Education Through ICT
- Served as the phd coordinator for 1 year
- Faculty advisor for the (2014-2018) batch and (2018 -2022 batch BE students
- project coordinator for the UG projects
- project coordinator for the PG VLSI and Embedded system
- Phd coordinator for the department.
- Served as the residential counselor in hostel from 2012-2014