Name :  Dr . S.P.Joy Vasantha Rani

Designation :  Professor

Educational Qualification :  M.E., Ph.D

Area of Specialization : VLSI, Signal processing, Reconfigurable Hardware architectures

Email ID :  This email address is being protected from spambots. You need JavaScript enabled to view it.

Phone : 044-22516240

 IRINS Profile

• Educational Qualifications

  Sl.No.	Examination Passed	Branch/Specialization	Year of Passing/ awarded	Institution where studied	University/ Board
  1)	PhD	VLSI	2009	Madras Institute of Technology, Anna University	Anna University
  2)	M.E	Power Electronics	1995	College of Engineering, Guindy, Anna University	Anna University
  3)	B.E	ECE	1993	Government College of Engineering, Tirunelveli, Madurai Kamaraj University	Madurai Kamaraj University

   

   

   

   

   

   

   

   

   

• Post Held

   

  Post Held	Period of Service		Name & Address of Employer
  	From	To
  Associate Professor	29-10-2015	Till date	MIT Campus, Anna University
  Assistant Professor	29-10-2008	28-10-2015	MIT Campus, Anna University
  Lecturer	8-7-2004	28-10-2008	MIT Campus, Anna University
  Teaching Research Associate	15-12-2000	7-7-2004	MIT Campus, Anna University
  Lecturer	19-7-1999	14-12-2000	Sri Muthukumaran Institute of Technology, Chennai-69
  Lecturer	26-6-1996	28-6-1999	National Engineering College, Kovilpatti

• Journals

   

  1. P., Joy Vasantha Rani, S.P., "Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms", Journal of Circuits, Systems and Computers, published by World Scientific Publishers. Vol. 2150081, (2020).
  2. C, S.P.Joy Vasantha Rani, "Performance Analysis of Intrinsic Embedded Evolvable Hardware using Memetic and Genetic Algorithms", International Journal of Bio-Inspired Computation (IJBIC), published by Inderscience Publishers. Vol. 15, Issue 1, pp. 43-51 (2020).
  3. R, Joy Vasantha Rani S.P, "Nonlinear Controller: Voltage Controlled PFC-Based Fuzzy MDPSM Controller with Predictive Input Voltage", Journal of Circuits, Systems and Computers, published by World Scientific. Vol. 2050207, (2020).
  4. Senthil Sivakumar, S.P.Joy Vasantha Rani, "Time domain modelled ADC BIST with ramp noise projection", International Journal of Electronics, published by Taylor & Francis. Vol. 106, Issue 8, pp. 1127-1140 (2019).
  5. Senthil Sivakumar, SP Joy Vasantha Rani, "Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation", Journal of Circuits, Systems and Computers, published by World Scientific. Vol. 28, Issue 3, pp. 1950042 (2019).
  6. C, SP Joy Vasantha Rani, "A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware–Software Co-Design", Journal of Circuits, Systems and Computers, published by World Scientific. (2019).
  7. Senthil Sivakumar & S.P.Joy Vasantha Rani, "Design of Linear Ramp Generator and Digital ORA for an area efficient high speed ADC BIST", Journal of Electrical Engineering, published by Politehnica Publishing House. (2018).
  8. Senthil Sivakumar, SP Joy Vasantha Rani, "An ADC BIST using on-chip ramp generation and digital ORA", Microelectronics Journal, published by Elsevier. Vol. 81, pp. 8-15 (2018).
  9. Senthil Sivakumar M and Joy Vasantha Rani.S.P."An area efficient, high-frequency digital built-in self-test for analogue to digital converter", International Journal of Electronics, 105:8, 1319-1330, DOI: 1080/00207217.2018.1440431 (2018)
  10. Indhumathi, S.P.Joy Vasantha Rani, "Remote fault diagnosis for distribution substation using Bayesian probabilistic matrix", Journal of Computational and Theoretical Nanoscience , published by American Scientific Publishers. Vol. 14, Issue 7, pp. 3463-3471 (2017).
  11. K, Joy Vasantha Rani.S.P and Kithikadevi. N, "Achievement of Cascaded Multirate FIR Filter Structures with CSE and CSD", Journal of Electrical Engineering, published by Politehnica Publishing House. Vol. 17, Issue 2, pp. 1 - 13 (2017).
  12. Prasanna, SC & Joy Vasantha Rani, SP, " Area and speed efficient implementation of symmetric FIR digital filter through reduced, parallel LUT decomposed DA approach", Circuits and Systems, published by Scientific Research Publishing. Vol. 7, Issue 8, pp. 1379-1391 (2016).
  13. S.C.Prasanna, S.P.Joy Vasantha Rani, " An efficient Implementation of Reconfigurable Interpolation Root-Raised Cosine FIR filter for SDR Application", Sadhana - AcademyProceedings in Engineering Science(Accepted), published by Springer. (2016).
  14. C.Ranjith, S.P.Joy Vasantha Rani, B.Priyadharshini, Medhuna Suresh and M.Madhusudhanan, "Optimizing GA operators for system evolution of Evolvable Embedded Hardware on Virtex 6 FPGA", ARPN journal of Engineering and applied sciences, Vol. 10, Issue 11, pp. 4908-4914 (2015).
  15. J.Britto Pari and S.P.Joy Vasantha Rani, "An optimized Architecture for Adaptive Digital Filter", ARPN journal of Engineering and applied sciences, Vol. 10, Issue 11, pp. 4964 - 4970 (2015).
  16. S.P.Joy Vasantha Rani, J.Samson and P.Vishak, "Dynamic Reconfigurable Architecture design of Viterbi Decoder", International journal of Applied Engineering Research, published by RIP Publications. Vol. 10, Issue 60, pp. 86 - 92 (2015).
  17. S.C.Prasanna and S.P.Joy Vasantha Rani, "Universal Programmable Modulator Architecture For Software Defined Radio", International journal of Applied Engineering Research, published by RIP Publications. Vol. 10, Issue 9, pp. 8854-8860 (2015).
  18. D.C.Diana, S.P.Joy Vasantharani, T.R. Nithya. and B.Srimukhee, "Adaptive Inertia Weight Particle Swarm Optimization For Linear and Nonlinear Channel Equalization", International Journal Of Scientific Research(IJSR), published by The Global Journals, India. Vol. 3, Issue 4, pp. 27-30 (2014).
  19. Britto Pari. J and Joy Vasantha Rani.S.P., "A Comparative Study on LUT and Accumulator Radix-4 Based Multichannel RNS FIR Filter Architectures", International Journal of Engineering and Technology (IJET), Vol. 6, Issue 2, pp. 735-744 (2014).
  20. Britto Pari. J and Joy Vasantha Rani.S.P., "Reconfigurable architecture of RNS based high speed FIR filter", Indian journal of Engineering and Material sciences(IJEMS), Vol. 21, pp. 233-240 (2014).
  21. Joy Vasantha Rani.S.P., "Pipelined Hardware design of Self Tuning Controller with On-chip Parameter Estimator", International journal of High Performance Systems Architecture (IJHPSA), published by Inderscience Publishers. (2014).
  22. Britto Pari. J and Joy Vasantha Rani.S.P., "FPGA Implementation of Adaptive Filter using Optimized Parallel FIR Filter ", International Journal of Computer Applications in Engineering, Technology and Sciences (IJ-CA-ETS) , Vol. 6, Issue 2, pp. 63-67 (2014).
  23. K.Mariammal, S.P.Joy Vasantha Rani and M.Banupriya, "Area Reduction using Farrow based Multirate Filter structure for Sampling rate conversion from CD to DAT", International journal of Applied Engineering Research, published by RIP Publications. Vol. 9, Issue 20, pp. 4722 - 4727 (2014).
  24. S.C.Prasanna and S.P.Joy Vasantha Rani, "Design of Transmitter for SDR application", International Journal of Advent research in Computer and Electronics (IJARCE), Vol. 1, Issue 7, pp. 36-42 (2014).
  25. S.P.Joy Vasantharani and K.Aruna Prabha, "Stochastic Logic Computation based RBFNN with Adaptive Hidden Layer Structure", Journal of Engineering, Design and Technology, published by Emarald publications. Vol. 8, pp. 206-220 (2010).
  26. S.P.Joy Vasantharani, P.Kanagasabapathy and L.Suganthi, " FPGA based Floating point Hardware design of recursive K-Means clustering algorithm for RBF neural network", International Journal of Intelligent Systems Technologies and Applications(IJISTA), published by Inderscience Publishers. Vol. 6, Issue 1, pp. 61-76 (2009).
  27. S.P.Joy Vasantharani, P.Kanagasabapathy, "Pipelined Floating Point hardware for Adaptive RBFNN Control", International journal of Systemics, Cybernetics and Informatics, pp. 23-30 (2008).

• Conferences

  1. Sudhanya, S.P.Joy Vasantha Rani, MC Lavanya, "Design of Logic Blocks for Efficient Architecture of FPGA" presented in a International level conference on IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP), organised by VIT Chennai, India from 04-Jul-2019 to 05-Jul-2019
  2. Thangam, S.P.Joy Vasantha Rani, "Voltage Controlled PFC Based Interleaved Synchronous Buck Converter BLDC motor" presented in a International level conference on 2019 IEEE 1st International Conference on Energy, Systems and Information Processing (ICESIP), India from 04-Jul-2019 to 05-Jul-2019.
  3. V.Karpagam, M.Senthil Sivakumar, S.P.Joy Vasantha Rani, "Effect of Ramp slope error in an on-chip ADC BIST" presented in a International level conference on 4th International conference on Science and Technology(ICONSET), organised by Jeppiar Engineering College, Chennai, India from 23-Mar-2018 to 24-Mar-2018.
  4. Jancy, Sudhanya.P, S.P.Joy Vasantha Rani, "Hybrid PSO-SA Algorithm for FPGA Placement" presented in a International level conference on 4th International Conference on Science and Technology(ICONSET), organised by Jeppiar Engineering College, Chennai, India from 23-Mar-2018 to 24-Mar-2018.
  5. Ashwini, M.Senthil Sivakumar, P.Joy Vasantha Rani, "Design of Linear Ramp Generator for ADC" presented in a International level conference on ICSCN -4th International Conference on Signal processing, Communication and Networking, organised by MIT, Chennai, India from 16-Mar-2017 to 18-Mar-2017.
  6. Jayashree, Ranjith.C, S.P.Joy Vasantha Rani, "A VLSI Implementation of an Adaptive Genetic Algorithm Processor" presented in a International level conference on ICSCN -4th International Conference on Signal processing, Communication and Networking, organised by MIT, Chennai, India from 16-Mar-2017 to 18-Mar-2017.
  7. Thangam, S.P.Joy Vasantha Rani, "Comparative analysis of PWM/PFM controlled SMPS using Matlab Simulink" presented in a International level conference on 4th International Conference on Signal Processing, Communication and Networking, ICSCN 2017, organised by Madras Institute of Technology, Chrompet, India from 16-Mar-2017 to 18-Mar-2017.
  8. Senthil Sivakumar, S.P. Joy Vasantha Rani, "Design of digital Built-In Self-Test for Analog to Digital Converter" presented in a International level conference on 10th International Conference on Intelligent Systems and Control (ISCO 2016), organised by Karpagam College of Engineering, Chennai,, India, pp.821-826 from 07-Jan-2016 to 08-Jan-2016.
  9. Krishnaveni, C. Ranjith and S.P. Joy Vasantha Rani, "Evolvable Hardware Architecture Using Genetic Algorithm for Distributed Arithmetic FIR Filter", Artificial Intelligence and Evolutionary Computations in Engineering Systems. Advances in Intelligent Systems and Computing, published by SPRINGER. Vol. 517, pp. 295-304 (2017).
  10. S, Senthil Sivakumar.M, S.P.Joy Vasantha Rani, "Design of Linear Ramp Generator for ADC" presented in a International level conference on ICSCN -4th International Conference on Signal processing, Communication and Networking, organised by MIT, Chennai, India from 16-Mar-2017 to 18-Mar-2017.
  11. Senthil Sivakumar and S. P. Joy Vasantha Rani, "Design of digital Built-In Self-Test for Analog to Digital Converter" presented in a International level conference on 10th International Conference on Intelligent Systems and Control (ISCO 2016), organised by Karpagam College of Engineering, Chennai,, India, pp.821-826 from 07-Jan-2016 to 08-Jan-2016.
  12. C.Ranjith and S.P.Joy Vasantha Rani, "A Hardware Implementation of Evolvable Embedded System for Combinational Logic Circuits using Virtex 6 FPGA" presented in a International level conference on 1st International Conference on Nano- electronics, Circuits and Communication Systems (NCCS – 2015), organised by ARTTC, BSNL, Ranchi, Jharkhand, India from 09-May-2015 to 10-May-2015.
  13.  D.C. Diana and S.P.Joy Vasantha Rani, "Modified PSO based Equalizers for Channel Equalization" presented in a International level conference on 1st International Conference on Nano- electronics, Circuits and Communication Systems (NCCS – 2015), organised by ARTTC, BSNL, Ranchi, Jharkhand, India from 09-May-2015 to 10-May-2015.
  14. K.Mariammal, S.P.Joy Vasantharani,, "Design and analysis of Fast convolution based Multirate Filter Banks" presented in a International level conference on 1st International Conference on Nano-electronics, Circuits and Communication Systems (NCCS – 2015), organised by ARTTC, BSNL, Ranchi, Jharkhand, India from 09-May-2015 to 10-May-2015.
  15. S.P.Joy Vasantha Rani, Samson, Vishak, "Dynamic Reconfigurable architecture design of Viterbi Decoder" presented in a International level conference on International conference on Architecture Software systems and Green Computing, organised by AVIT, Chennai, India from 07-May-2015 to 08-May-2015.
  16. C.Indumathi and S.P.Joy Vasantha Rani, "A Fuzzy based Fault Type Detector for Remote Fault diagnosis of Distribution Feeders" presented in a International level conference on 3rd International Conference on Signal processing, Communication and Networking (ICSCN), organised by MIT, Chrompet, India from 26-Mar-2015 to 28-Mar-2015.
  17.  J.Britto Pari, S.P.Joy Vasantha Rani, "FPGA Realization of Multiplierless FIR filter Architectures" presented in a International level conference on 3rd International Conference on Signal processing, Communication and Networking (ICSCN), organised by MIT, Chrompet, India from 26-Mar-2015 to 28-Mar-2015.
  18.  K.Mariammal, S.P.Joy Vasantharani,, "Hardware Implementation of Speech Recognition and validation using Arduino Leonardo Board" presented in a International level conference on International Conference on Emerging Trends in Information Technology(ICETIT’15), India from 09-Mar-2015 to 10-Mar-2015.
  19. "Evolvable Hardware: A New Trend in the Design of Digital VLSI Systems" presented in a International level conference on 8th International Conference on Advanced Computing and Communication Technologies (ICACCT-2014), India from 05-May-2014.
  20.  S.Balamurali, S.P.Joy Vasantha Rani, "LUT based design of Adaptive Filter for Digital Hearing Aid applications" presented in a International level conference on International conference on Computer science and Engg(ICCSE), India from 14-Apr-2014 to 15-Apr-2014.
  21. D.C. Diana and S.P. Joy Vasantha Rani, "Improved Particle Swarm Optimization Algorithm for Adaptive Equalization" presented in a International level conference on International Conference on Mathematical Computer Engineering, organised by VIT, Chennai, India from 29-Nov-2013 to 30-Nov-2013.
  22. K.Mariammal, S.P.Joy Vasantha Rani and T.Kohila, "Area efficient high speed low power multiplier architecture for multirate filter design" presented in a International level conference on IEEE International conference on Emerging Trends in Computing, Communication and Nanotechnology, India from 25-Mar-2013 to 26-Mar-2013.
  23.  J.Britto Pari, S.P.Joy Vasantha Rani, "Reconfigurable RNS FIR filter Using Higher Radix Multiplier" presented in a International level workshop on Third International Workshop on VLSI (VLSI 2012), Chennai, India from 13-Jul-2012 to 15-Jul-2012.
  24. Harish, S. and Joy Vasantha Rani.S.P., "A dynamic partial reconfigurable FIR filter architecture" presented in a International level conference on International Conference on Recent Trends In Information Technology (ICRTIT), organised by MIT, India from 19-Apr-2012 to 21-Apr-2012.
  25.  Katna Radha and S.P.Joy Vasantha Rani, "High speed Reed Solomon decoder using Galois field Arithmetics" presented in a National level conference on Proceedings of National Conference on Signal Processing, Communications and VLSI design (NCSCV'09), India from 22-May-2009 to 24-May-2009.
  26.  Aruna Prabha K., Joy Vasantha Rani S.P., "Hardware implementation of RBF neural network algorithms integrated with stochastic logic theory for control applications" presented in a International level conference on System analysis and information technologies: Materials of the X International Conference on Science and Technology, Kyiv, Ukraine from 20-May-2008 to 24-May-2008.
  27.  S.P.Joy Vasantha Rani, P.Kanagasabapathy, "Pipelined Floating-point Hardware of On-chip Parameter Estimator for Self Tuning Control" presented in a International level conference on Sensors, Signal Processing,Communication, control and Instrumentation(SSPCCIN), organised by Vishwakarma Institute of Technology, Pune, India from 03-Jan-2008 to 05-Jan-2008.
  28.  S.P.Joy Vasantha Rani, P.Kanagasabapathy, "Multilayer perceptron neural network architecture using VHDL with combinational logic Design of Sigmoid Function" presented in a International level conference on ICSCN, organised by MIT, India from 22-Feb-2007 to 24-Feb-2007.
  29. organised by CEG, Anna University, India from 01-Jun-2006 to 02-Jun-2006.
  30. S.P.Joy Vasantha Rani, P.Kanagasabapathy, "Digital Fuzzy logic controller using VHDL" presented in a International level conference on INDICON, organised by IIT, Chennai, India from 11-Dec-2005 to 13-Dec-2005.
  31. Joy Vasantha Rani S.P., Kanagasabapathy.P, "Design of Neural Network on FPGA" presented in a International level conference on International Conference on VLSI (VLSI’04), Las Vegas, Neveda,USA from 21-Jun-2004 to 24-Jun-2004.
  32. L.Suganthi, S.P.Joy Vasantha Rani, "Floating point hardware architecture of RBF neural network for adaptive control applications" presented in a National level conference on National conference on Information, communication and computing(NCICC'2007), organised by CEG campus, India .
  33. T.Anbanandhan, S.P.Joy Vasantha Rani, "High speed parallel implementation of current mode multiplier/divider for signal processing applications" presented in a National level conference on National conference on Information, communication and computing(NCICC'2007), organised by CEG campus, India . 

• Invited Lectures

  1. Delivered a Lecture on "Designing Arithmetic Building Blocks" in FDTP on VLSI Design-EC6601 organized by Department of Electronics Engineering, MIT, Chennai (24-Nov-2017).
  2. Delivered a Lecture on "Embedded SOC platform on FPGA" in Workshop on "EMBEDDED SOC DESIGN" organized by Department of Electronics Engineering, MIT Campus,, Chrompet, Chennai (08-Mar-2016).
  3. Delivered a Lecture on "CMOS Technology and HDL Programming" in Guest Lecture for students organized by Vel Tech Rangarajan Dr.Sagunthala R&D Institute of, Chennai (16-Oct-2015).
  4. Delivered a Lecture on "Microprocessors and Microcontrollers" in FDP Programme organized by Sri Sastha Institute of Engineering and Technology, Chennai (16-Jun-2014).
  5. Delivered a Lecture on "Sequential Circuits" organized by RMK Engineering College, Chennai (16-Feb-2013).
  6. Delivered a Lecture on "Realization of FIR filters" in FDTP on EC2302 Digital Signal Processing organized by Department of Electronics Engineering, MIT campus, Chrompet (17-Jun-2013).
  7. Delivered a Lecture on "DFT and its properties" in FDTP on EC2302 Digital Signal Processing organized by Department of Electronics Engineering, MIT campus, Chrompet (19-Jun-2013).
  8. Delivered a Lecture on "Digital Principles and Digital VLSI" in Guest Lecture organized by University College of Engineering, Tindivanam, India (25-Oct-2012).

• Programme Organised

  1. Coordinator, National level workshop on "UGC Sponsored Two Days Workshop On “Embedded SOC Design"" from 07-Mar-2016 to 08-Mar-2016.
  2. Coordinator, National level Short Course on "FDTP on VLSI Design" from 09-Dec-2013 to 15-Dec-2013.
  3. Coordinator, National level workshop on ""Two days workshop on "Analog IC design"" from 14-Sep-2012 to 15-Sep-2012.
  4. Coordinator, National level workshop on "Two days workshop on "Development of Embedded system using C for ARM with extensive hands on Experience"" from 07-Jan-2010 to 08-Jan-2010. 

• Programme Attended

  27. Participated in a National level workshop on "Advanced Digital Design Flow using Cadence" organized by MIT Chennai, India from 01-Mar-2018 to 03-Mar-2018.

  26. Participated in a National level workshop on "One week Short term course on "Professional Ethics and Values"" organized by NITTTR, Chennai, India from 27-Nov-2017 to 01-Dec-2017.

  25. Participated in a International level workshop on "FDP on Student Evaluation and Question Paper Setting" organized by MIT Campus, Anna University, India from 13-Oct-2016 to 15-Oct-2016.

  24. Participated in a International level conference on "International conference on Architecture, Software systems and Green computing(ICASG 2015)" organized by AVIT, Chennai, India from 07-May-2015 to 08-May-2015.

  23. Participated in a National level workshop on "Advancements in Biomedical Signal and Image Processing (UGC-DRS-II(SAP-II) sponsored)" organized by Dept. of Electronics Engineering, MIT campus, Anna University, India from 29-Oct-2015 to 30-Oct-2015.

  22. Attended a International level Short Course on "Two week ISTE STTP on "Introduction to Design of Algorithms"" organized by IIT, Kharagpur, India from 27-Apr-2015 to 30-May-2015.  

  21. Participated in a International level conference on "3rd International Conference on Signal processing, Communication and Networking (ICSCN)" organized by MIT, Chrompet, India from 26-Mar-2015 to 28-Mar-2015.

  20. Participated in a National level workshop on "Image Processing framework using FPGA" organized by MIT, India from 15-Oct-2012 to 16-Oct-2012.

  19. Participated in a National level workshop on "Basic Electronics" organized by IIT, Bombay, India from 28-Jun-2011 to 08-Jul-2011.

  18. Participated in a National level workshop on "E-Learning for Engineering Educators" organized by MIT, India from 24-Jun-2011 to 25-Jun-2011.

  17. Participated in a National level workshop on "VLSI for signal processing" organized by MIT, India from 14-Mar-2011 to 15-Mar-2011.

  16. Attended a National level seminar on "Guidelines to sponsored research projects" organized by Dhanalakshmi Engineering college, India from 06-May-2010.

  15. Participated in a National level workshop on "Effective teaching/ learning of computer programming" organized by IIT, Bombay, India from 14-Dec-2009 to 24-Dec-2009.

  14. Participated in a International level conference on "International conference on Advanced computing" organized by MIT, India from 13-Dec-2009.

  13. Attended a National level Short Course on "Faculty development training program on Web technology" organized by MIT, India from 01-Dec-2009 to 07-Dec-2009.

  12. Participated in a National level workshop on "high speed digital design and testing" organized by MIT, India from 23-Oct-2009. 11. Participated in a International level workshop on "Content based image retrieval and fusion" organized by MIT, India from 07-Aug-2009 to 09-Aug-2009.

  10. Participated in a International level conference on "Intelligent agent and multi-agent systems" organized by AVIT, India from 22-Jul-2009 to 24-Jul-2009.

  9. Participated in a National level workshop on "Embedded Systems Development on FPGAs" organized by MIT, India from 07-Jan-2008 to 08-Jan-2008.

  8. Participated in a International level conference on "International Conference on Sensors, Signal Processing, Communication, Control and Instrumentation (SSPCCIN) " organized by Vishwagarma Institute of Technology, Pune, India from 03-Jan-2008 to 05-Jan-2008.

  7. Attended a National level Short Course on "Training Program on ARM Processor based Development System" organized by MIT, India from 23-May-2007 to 24-May-2007.

  6. Participated in a International level conference on "International Conference on Signal Processing, Communication and Networking(ICSCN)" organized by MIT, India from 22-Feb-2007 to 24-Feb-2007.

  5. Participated in a National level workshop on "Continuing Education Programme on Embedded systems and technology" organized by IIT, Karagpur, India from 19-Jun-2006 to 24-Jun-2006.

  4. Participated in a National level conference on "2nd National Conference on Signals, systems and Communication(NCSSC)" organized by Department of ECE, CEG campus, Anna University, India from 01-Jun-2006 to 02-Jun-2006.

  3. Participated in a International level conference on "International Conference INDICON " organized by IEEE Madras section at IIT Madras, India from 11-Dec-2005 to 13-Dec-2005.

  2. Attended a National level Short Course on "A refresher course on VLSI design" organized by MIT, India from 28-Mar-2005 to 29-Mar-2005.

  1. Attended a National level Short Course on "AICTE-ISTE Short term training programme on Trend in Intelligent Measurement and control" organized by MIT from 22-Nov-2004 to 27-Nov-2004.

   

   

• Membership

  MEMBERSHIP IN PROFESSIONAL ORGANIZATION

  • ISTE
  • IETE

• Research Guidance

  Ph.D completed as supervisor : 8

  Ph.D on going as Supervisor : 1

  Ph.D on going as Joint supervisor : 2

   

  Sl.No	Name of the Scholar	Topic	Mode	Year of completion
  1.	J.Britto Pari	Efficient digital filter architectures for multichannel filtering and adaptive filtering techniques	Full Time	2016
  2.	D.C.Diana	Investigation of Swarm Intelligence techniques to enhance Channel Equalization	Part Time	2017
  3.	S.C.Prasanna	Reconfigurable and dedicated FIR filters, Interpolators and modulators for SDR	Part Time	2017
  4.	K.Mariammal	Multiplierless Implementation of Area Efficient Multirate FIR filter structures for Sampling Rate Conversion	Part Time	2018
  5.	M.Senthil Sivakumar	Design of Built-In Self-Test for Analog to Digital Converter with Static Error Modeling and Calibration	Full Time	2019
  6.	C. Indhumathi	Intelligent Fault Location, Isolation and Service Restoration in Distribution System	Part Time	2019
  7.	R.Thangam	Digital Pulse Skipping Modulation Strategies for DC-DC Converters to improve the Power Conversion Efficiency at Partially Loaded Conditions and incorporation of PFC	Part Time	2020
  8.	Ranjith C	Embedded Evolvable Hardware Design of Digital Circuits using Bio-inspired Algorithms	Part Time	2020
  9.	P.Sudhanya	Efficiency Enhancement of FPGA Architecture	Full Time	On Roll

   

   

• Subjects Handled

  PG Subjects:

  • Design For Testability
  • VLSI Architectures for System Design
  • Hardware – Software Codesign for Embedded system
  • VLSI for Signal Processing
  • PC and Microcontroller based system Design

  UG Subjects:

  • Digital System Design
  • VLSI Design
  • Microprocessors and Microcontrollers
  • Computer Architecture and Organisation
  • Digital Electronics for system Design
  • Electronics Circuits II
  • Power Electronics
  • Advanced Microprocessors
  • Analog Electronics

• Projects Undertaken

  1. “Performance Enhancement in FPGA Architecture by Efficient design of Logoc Blocks” sponsored by DST – Women Scientist Scheme A(WOS - A), 2018-2021. Scientist Mentor: Dr.S.P.Joy Vasantha Rani, Associate Professor. Principal Investigator: Ms.P. Sudhanya, Research Scholar, Dept of Electronics Engineering, MIT Campus. Project Cost: 17.8 Lakhs.
  2. "Sound of Actions – A Technical Aid for Speaking Disabled", funded by CTDT Research Support Scheme by Anna University (Mar. 2014 - Dec. 2014).. Project Cost: 25000.00.
  3. "Harassment Emergency Rescuer(HER)", funded by CTDT Research Support Scheme by Anna University (Mar. 2015 - Dec. 2015).. Project Cost: 25000.00.
  4. "FPGA based real time visual static hand gesture recognition system", funded by CTDT Research Support Scheme by Anna University (Mar. 2016 - Dec. 2016) (December-1969 - December-1969). Project Cost: 25000.00.

• Additional Responsibilities

  Institute level:

  • Deputy Warden, Girls Hostel, Anna University, Chennai from May-2019.
  • Selection Committee Member To Recruit Project staff, Sponsored Projects, CTDT, 2015-2016, Anna University, Chennai.
  • Additional Chief Superintendent for end semester examinations for UG students during Apr./May 2010.

  Department level:

  • Department NAAC Coordinator, Department of Electronics Engineering, Anna University, Chennai from May-2019.
  • IQAC Department Coordinator, Department of Electronics Engineering, Anna University, Chennai from May-2019.
  • Syllabus committee member of M.E. VLSI design and Embedded system (2015 CBCS Regulation) and contributed in framing the curriculum and the syllabus.
  • Departmental Consultative Committee (DCC) member in the dept. of Electronics Engineering, 2012-2015
  • Purchased FPGA development boards and testing equipments worth Rs. 35 Lakhs – under  DST-FIST 2012-2017
  • Guiding UG  and PG project students.
  • Class committee chairman for UG students from 2012 - 2016.
  • UG Syllabus Revision Committee Member for 2012 regulation.
  • Involved in purchase activities for purchasing VLSI products, Microprocessors and microcontrollers during 2011.
  • President of Electronics Engineering Association (EEA) in the academic year 2009-10. On behalf of the EEA, six workshops have been organized for students during Electrofocus 2010.
  • Faculty advisor for NRI students in the academic year 2009-10.

Name : Dr. P.T.V. Bhuvaneswari

Designation  : Professor

Qualification  :  Ph.D

Area of Specialization : Wireless Sensor Network, Wireless Network, Wireless Communication

E-mail Id : This email address is being protected from spambots. You need JavaScript enabled to view it.   

IRINS Profile

• Educational Qualification

  Sl.No.	Examination Passed	Name of the University/Board	Year of Passing/ awarded	Subject/ Specialization
  1)	Ph.D	MIT, Anna University	(2006 - 2011)	wireless sensor network
  2)	M.E	Government College of Technology	(1998 - 2000)	Applied Electronics
  3)	B.E	St. Peters Engineering College, Madras	(1993 - 1997)	ELECTRICAL AND ELECTRONICS ENGINEERING

   

   

   

   

   

   

   

   

   

• Post Held

  Post held	Period of Service		Name & Address of Employer
  	From	To
  Professor	Feb-2018	till date	Department of Electronics Engineering, Madras Institute of Technology, Anna University, Chennai
  Assistant Professor	July-2004	Jan-2018	Department of Electronics Engineering, Madras Institute of Technology, Anna University, Chennai
  Lecturer	4 Years		Sathyabama Institute of Technology, Chennai

   

   

• Research Index

   

   

  Citation index                    :        77

  H-Index                            :        5

  I10 Index                          :        3

   

• Journals

   

   

  8.	"Stray Dog Detection In Wired Camera Network", ICTACT Journal on Image And Video Processing, published by Government of Tamil Nadu. Vol. 4, Issue 1, pp. 642-646 (2013).
  7.	P.T.V.Bhuvaneswari and V. Vaidehi, " Real Time Validation of Efficient Received Signal Strength Based Localization Algorithm in Wireless Sensor Network", Journal on Ad Hoc & Sensor Wireless Networks, published by Old City Publishing. pp. 1-27 (2013).
  6.	M.Rehena Sulthana P.T.V.Bhuvaneswari N.Rema, "Routing Protocols in 6LoWPAN: A Survey", European Journal of Scientific Research, published by Scientific Research Platform. Vol. 85, Issue 2, pp. 248 -261 (2012).
  5.	M. Rehenasulthana, P. T. V. Bhuvaneswari, N. Rama, " Enhanced Location Based Routing Protocol for 6LOWPAN", Journal on Computer Networks and Communication , published by Academy & Industry Research Collaboration Center. Vol. 4, Issue 3, pp. 93-108 (2012).
  4.	P.T.V.Bhuvaneswari, V. Vaidehi and M.Agnes Saranya, " Distance Based Transmission Power Control scheme for Indoor Wireless Sensor Network", Springer Journal (LNCS) Special Issue on Security in Computing of Transactions on Computational Sciences XI, published by Springer. Vol. 6480, pp. 207-222 (2011).
  3.	P.T.V.Bhuvaneswari, and V.Vaidehi, " An Efficient Distance Estimation Algorithm for Indoor Sensor Network", International Journal of Computer Theory and Engineering (IJCTE), , published by International Association of Computer Science an. Vol. 3, Issue 6, pp. 797-801 (2011).
  2.	Bhuvaneswari.P.T.V, and Vaidehi.V, " Location aided energy efficient routing protocol in wireless sensor network", International Journal of Simulation: Systems, Science & Technology (IJSSST), published by United Kingdom Simulation Society. Vol. 11, Issue 4, pp. 41-50 (2010).
  1.	P.T.V.Bhuvaneswari, and Vaidehi V, " Enhancements Techniques Incorporated in LEACH- A Survey", Indian Journal of Science and Technology, published by Informatics (India) Ltd - Indian Society for Edu. Vol. 2, Issue 5, pp. 36-44 (2009).

• Conferences

   

  41.	"Performance Analysis of 4G LTE-A networks for Dynamic Cell Range Expansion" presented in a National level conference on 8th National Conference on Signal Processing, Communication and VLSI Design (NCSCV’16), organised by ANNA UNIVERSITY REGIONAL CAMPUS, COIMBATORE, INDIA from 29-Apr-2016 to 30-Apr-2016.
  40.	"Lagged Correlation Based Event Detection Algorithm for Level Crossing Safety System" presented in a International level conference on Third International Conference on electronics and Communication System (ICECS-2016), organised by Karpagam College of Engineering, INDIA from 25-Feb-2016 to 26-Feb-2016.
  39.	"A Study on Handover Parameter Optimisation in LTE-A Networks" presented in a International level conference on TEQIP-II Sponsored IEEE International Conference on Microelectronics, Computing and Communication (MicroCom 2016), organised by NIT Durgapur, West Bengal, INDIA from 23-Jan-2016 to 26-Jan-2016.
  38.	"Ultrasonic Sensor based railway track occupancy detection" presented in a International level conference on IEEE- Seventh International conference on Computation Intelligence & Communication Networks(CICN 2015), organised by MRI LAB, INDIA from 12-Dec-2015 to 14-Dec-2015.
  37.	P.T.V.Bhvaneswari, R. Meenupriya, "A Dynamic Cell Range Expansion Scheme in 4G LTE Networks" presented in a National level conference on 7th National Conference on Signal Processing, Communication and VLSI Design (NCSCV’ 15), organised by ANNA UNIVERSITY REGIONAL CAMPUS, COIMBATORE, INDIA from 24-Apr-2015 to 25-Apr-2015.
  36.	"Real-Time Implementation of Low Cost ZigBee Based Motion Detection System" presented in a International level conference on IEEE- Fifth International Conference on Communication Systems and Network Technologies (CSNT 2015), organised by MRI lab, Chitkara university, INDIA from 04-Apr-2015 to 06-Apr-2015.
  35.	"Throughput Analysis of a LTE System for Static Environment" presented in a International level conference on International Conference on Signal Processing, Communication and Networking (ICSCN 2015), organised by MIT Campus, Anna University, INDIA from 26-Mar-2015 to 28-Mar-2015.
  34.	"An Analysis on Cell Range Expansion in 4G LTE Networks" presented in a International level conference on International Conference on Signal Processing, Communication and Networking (ICSCN 2015), organised by MIT Campus, Anna University, INDIA from 26-Mar-2015 to 28-Mar-2015.
  33.	"Fuzzy Based Intelligent System for Human Activity Monitoring" presented in a International level conference on IEEE International Conference on Intelligent Information Technologies (ICIIT 2014), organised by Anna University, INDIA from 11-Dec-2014 to 13-Dec-2014.
  32.	. "Activity Estimation Using Regression Techniques" presented in a International level conference on IEEE -Sixth International Conference on Computational Intelligence and Communication Networks (CICN 2014),Udaipur, Rajasthan, organised by Machine Intelligence Research Labs association with IEEE, INDIA from 14-Nov-2014 to 16-Nov-2014.
  31.	P.T.V.Bhuvaneswari and Saraswathi Priyadharshini , "Activity Estimation Using Regression Techniques" presented in a International level conference on IEEE International Conference on Computational Intelligence and Communication Networks (CICN 2014), organised by IEEE computer society, Udaipur, Rajasthan, INDIA from 14-Nov-2014 to 16-Nov-2014.
  30.	. "An Experimental Analysis to Study the Characteristic Features of Gas Sensor" presented in a International level conference on Fourth International Conference on Information Communication and Embedded Systems (ICICES 2014), organised by S.A.Engineering College, INDIA from 27-Feb-2014 to 28-Feb-2014.
  29.	"Multivariate Linear regression based activity recognition and classification" presented in a International level conference on Fourth International Conference on Information Communication and Embedded Systems (ICICES 2014), organised by S.A.Engineering College, INDIA from 27-Feb-2014 to 28-Feb-2014.
  28.	"Comparative Study On Decision Tree Based Data Mining Algorithm To Assess Risk Of Epidemic" presented in a International level conference on Fourth International Conference on Sustainable Energy and Intelligent System (SEISCON 2013), organised by K.C.G College of Technology, INDIA from 12-Dec-2013 to 14-Dec-2013.
  27.	"Humanoid Robot Based Physiotherapeutic Assistive Trainer for Elderly Health Care" presented in a International level conference on International Conference on Recent Trends in Information Technology 2013, organised by MIT ANNA UNIVERSITY, INDIA from 25-Jul-2013 to 27-Jul-2013.
  26.	Meenupriya, marcia and P.T.V.Bhuvaneswari, "Remote Access of Home Appliances Using Humanoid Robot" presented in a International level conference on International Conference on Recent Trends in Information Technology 2013, organised by MIT ANNA UNIVERSITY, INDIA from 25-Jul-2013 to 27-Jul-2013.
  25.	"Real Time Implementation of Humanoid Robot Based Intelligent Child Interactive System" presented in a International level conference on 2013 International Conference on Communication Systems and Network Technologies (CSNT 2013), organised by IEEE -gwalior, INDIA from 06-Apr-2013 to 08-Apr-2013.
  24.	"An Efficient Mobility Based Localization in Underwater Sensor Networks" presented in a International level conference on Fourth International Conference on Computational Intelligence and Communication Networks (CICN 2012), organised by GLA University Mathura, Uttar Pradesh, INDIA from 03-Nov-2012 to 05-Nov-2012.
  23.	"Adaptive Traffic Signal Flow Control Using Wireless Sensor Networks" presented in a International level conference on Fourth International Conference on Computational Intelligence and Communication Networks (CICN 2012), organised by GLA University Mathura, Uttar Pradesh, INDIA from 03-Nov-2012 to 05-Nov-2012.
  22.	Thavamalar Vinola and P.T.V.Bhuvaneswari, "An Efficient Localized Voronai Algorithm for Obstacle Detection in Wireless Sensor Networks " presented in a International level conference on International Conference on Recent Trends in Information Technology, organised by MIT ANNA UNIVERSITY, INDIA from 19-Apr-2012 to 21-Apr-2012.
  21.	Thirukurral, Vignesh, Jagan and P.T.V.Bhuvaneswari, , "Design of Intelligent Child Interactive System using Humanoid Robot " presented in a National level conference on SENNET 2012, organised by VIT UNIVERSITY, INDIA from 19-Jan-2012 to 21-Jan-2012.
  20.	Bhuvaneswari.P.T.V and Sabari Ganesh, "Enhanced Call Admission Control for WiMAX Networks " presented in a International level conference on International Conference on Recent Trends in Information Technology, organised by MIT ANNA UNIVERSITY, INDIA from 03-Jun-2011 to 05-Jun-2011.
  19.	M.Rehena Sultana, P.T.V.Bhuvaneswari and N.Rema, "A Survey on Routing Mechanism in 6LoWPAN Architecture" presented in a International level conference on SENNET 2012, organised by VIT UNIVERSITY, INDIA from 19-Jan-2011 to 21-Jan-2011.
  18.	P.T.V.Bhuvaneswari, Vaidehi V, Agnes Saranya, "Optimal Transmission Power Selection under Energy Constraints for Sensor Network Localization" presented in a International level conference on International Conference on Control, Automation, Robotics and Vision (ICARCV 2010) , organised by Nanyang Technological University & CSS & IEEE, SINGAPORE from 07-Dec-2010 to 10-Dec-2010.
  17.	"An Analytical Modeling Design to Select an An Analytical Modeling Design to Select an Optimal Forwarding Neighbor in Lossy Wireless Sensor Networks" presented in a International level conference on International Conference on Computational Intelligence and Communication Networks, organised by IEEE computer Society, Bhopal, INDIA from 26-Nov-2010 to 28-Nov-2010.
  16.	P.T.V.Bhuvaneswari, Jaivignesh and V.Vaidehi, "On-demand Location Aware Energy Efficient Routing in Wireless Sensor Networks" presented in a National level conference on National Conference in Electronics, Computers and Communications, INDIA from 07-Oct-2010 to 09-Oct-2010.
  15.	Bhargavi.R, V.Vaidehi, P.T.V.Bhuvaneswari, P. Balamurali, Girish Chandra, "Complex Event Processing for Object Tracking in Wireless Sensor Networks" presented in a International level conference on IEEE/WIC/ACM International Conference on Web Intelligence and Intelligent Agent Technology, organised by IEEE Computer Society Press, CANADA from 31-Aug-2010 to 03-Sep-2010.
  14.	P.T.V.Bhuvaneswari, Karthik and V.Vaidehi, "Dasarathy Model based Fusion Framework for fire detection application in WSN" presented in a International level conference on The Second International Conference on Wireless & Mobile Networks (WiMoN-2010), organised by springer, INDIA from 23-Jul-2010 to 25-Jul-2010.
  13.	P.T.V.Bhuvaneswari, V.Vaidehi, Agnes Saranya, "Localization based on Signal Strength using Kalman Approach" presented in a International level conference on The Second International Conference on Wireless & Mobile Networks (WiMoN-2010), organised by Springer, INDIA from 23-Jul-2010 to 25-Jul-2010.
  12.	P.T.V.Bhuvaneswari, Karthik and V.Vaidehi, "Development of Fusion Framework with impression Compensated Event based Wireless Sensor Network" presented in a National level conference on Advanced Pattern Mining and Multimedia Computing 2010, organised by National Institute of Technology , Trichy, INDIA from 06-Feb-2010 to 07-Feb-2010.
  11.	P. T. V. Bhuvaneswari ,R. Balakumar, V. Vaidehi and P. Balamuralidhar, "Solar Energy Harvesting for Wireless Sensor Networks" presented in a International level conference on First International Conference on Computational Intelligence, Communication System and Networks (CICSYN 2010), organised by IEEE Computer Society, INDIA from 23-Jul-2009 to 25-Jul-2009.
  10.	P.T.V.Bhuvaneswari, Sridevi and V.Vaidehi, "Performance analysis of MMSE based Data aggregation in wireless sensor network" presented in a International level conference on International conference on Wireless Networks (ICWN’09), organised by WorldCom, USA from 13-Jul-2009 to 16-Jul-2009.
  9.	P.T.V.Bhuvaneswari, and V.Vaidehi, "LMR: Localized Multicast Routing for Wireless Sensor Networks" presented in a International level conference on National Conference on Signal Processing, Communication and VLSI design (NCSCV ’09), organised by ANNA UNIVERSITY Technology, Coimbatore, INDIA from 08-May-2009 to 09-May-2009.
  8.	P.T.V.Bhuvaneswari, Neelakandan and V.Vaidehi, "Modified WBIP Multicast Routing Protocol for Wireless Sensor Networks" presented in a International level conference on second National Conference on Recent Research Trends in Advanced Computing, organised by Thiagarajar School of Management, INDIA from 17-Apr-2009 to 17-Apr-2009.
  7.	P.T.V.Bhuvaneswari, Sridhar and V.Vaidehi, "Node Deployment, Sensing Coverage, Packet Traffic Model and Information Generation Mechanisms for Wireless Sensor Networks" presented in a National level conference on Fourth National Conference on Signals, Systems and Communication, organised by CEG campus, Anna University, INDIA from 08-May-2008 to 09-May-2008.
  6.	P.T.V.Bhuvaneswari, Vaidehi V. and Shanmugavel S, "SPEAR: Sensor Protocol for Energy Aware Routing" presented in a International level conference on 3rd International Conference on wireless Communication and Sensor Network (WCSN 2007), organised by IIIT - Allahabad, INDIA from 13-Dec-2007 to 15-Dec-2007.
  5.	P.T.V.Bhuvaneswari, Balaji and V.Vaidehi, "Enhancement of DCF in 802.11" presented in a International level conference on International Conference on Signal Processing, Communication and Networking (ICSCN 2007), organised by MIT campus, Anna University, INDIA from 01-Dec-2007 to 04-Dec-2007.
  4.	P.T.V.Bhuvaneswari, Sangeetha and V.Vaidehi, "Traffic Aware Time-out MAC protocol for Wireless Sensor Network" presented in a National level conference on National Conference on Signals, Systems and Communication (NCSSC 06), organised by CEG campus, Anna University, INDIA from 01-Jun-2006 to 02-Jun-2006.
  3.	Jasmeen and P.T.V.Bhuvaneswari, "Energy Efficient and Secure MAC Protocol for Wireless Sensor Network," presented in a National level conference on National Conference CSIP, organised by JNEC, Aurangabad, INDIA from 01-Apr-2006 to 03-Apr-2006.
  2.	P.T.V.Bhuvaneswari, and V.Vaidehi, "Energy Efficient MAC protocol for Wireless Sensor Networks" presented in a International level conference on National Workshop on Current Trends in Communication and Networking (CTCN 2006), organised by MIT campus, Anna University, INDIA from 24-Feb-2006 to 25-Feb-2006.
  1.	"An Age Priority Packet Discarding scheme for ATM buffer Management" presented in a National level conference on National Conference on Communication and Networking (NCCN 2003), organised by SRM College, INDIA from 26-Feb-2003 to 28-Feb-2003.

• Books Authored

  1.

  "Introduction to Cognitive Radio Networks and Applications, Chapter - SPECTRUM SENSING IN COGNITIVE RADIO NETWORKS: A SURVEY" authored by Editor -Tomar, Bagwari, Kanti and Chapter author - Dr.P.T.V.Bhuvaneswari and published by Taylor & Francis, 6000 Broken Sound Parkway NW, Suite 300, Boca Rato.(2016)

• Invited Lectures

   

  6.	Delivered a Lecture on "Clustering in WSN" in Workshop on “Wireless Sensor Networks and Cloud Computing organized by MIT ANNA UNIVERSITY, INDIA (16-May-2011).
  5.	Delivered a Lecture on "Recent Trends in WSN" in AICTE –QIP Sponsored Short-term Course on Recent Trends in Computer Networks organized by Anna University, INDIA (18-Apr-2011).
  4.	Delivered a Lecture on "presidential address on Research Issues and Recent" in National Conference on “Research Issues and Recent Trends in Electronics and Communication organized by GKM college of Engineering and Technology, INDIA (25-Mar-2011).
  3.	Delivered a Lecture on "Overview of Wireless Networks" organized by St. Joseph’s College of Engineering, INDIA (05-May-2008).
  2.	Delivered a Lecture on "Data Aggregation in WSN" in National Level workshop on Wireless Sensor Networks organized by Eswari Engineering College, INDIA (29-Sep-2007).
  1.	Delivered a Lecture on "An Overview of WSN" in Three days community service workshop on Next Generation Wireless Networks organized by MIT ANNA UNIVERSITY, INDIA (20-Sep-2007).

   

• Current Sponsored Projects

   

  1.	"Architecture to analyze the Performance of 6lowpan Based Networks".. Project Cost: 42.00L.

• Sponsored Projects Completed

   

  4.	"Intelligent Child Interactive System", funded by CTDT ANNA UNIVERSITY (March-2012 - September-2012). Project Cost: 25000.00.
  3.	"Complex Event Processing for WSN", funded by DST NRDMS (March-2011 - March-2014). Project Cost: 2500000.00.
  2.	"Network Protocol for Wireless Sensor Network", funded by TEQIP (January-2007 - January-2008). Project Cost: 240000.00.
  1.	"Power optimization in Wireless Sensor Networks", funded by TCS BANGALORE (July-2008 - December-2010). Project Cost: 1075000.00.

• Programme Chaired

   

  8.	Chairman, International level conference titled "IEEE Wireless Communications, Signal Processing and Networking (WiSPNET), 2016" conducted by Sri Sivasubramaniya Nadar College of Engineering from 23-Mar-2016 to 25-Mar-2016.
  7.	Chairman, International level conference titled "International Conference on Recent Trends in Information Technology (ICRTIT 2014)" conducted by MIT campus, Anna University from 10-Apr-2014 to 12-Apr-2014.
  6.	Chairman, International level conference titled "International Conference on Recent Trends in Information Technology (ICRTIT 2013)" conducted by MIT campus, Anna University from 25-Jul-2013 to 27-Jul-2013.
  5.	Chairman, International level conference titled "International Conference on Recent Trends in Information Technology (ICRTIT 2012)" conducted by MIT campus, Anna University from 19-Apr-2012 to 21-Apr-2012.
  4.	International level conference titled "International Conference in Recent Trends in Information Technology, (ICRTIT 2011)" from 03-Jun-2011 to 05-Jun-2011.
  3.	International level conference titled "IEEE sponsored International Conference on “Computational Intelligence and Communication Networks (CICN 2010)" from 26-Nov-2010 to 28-Nov-2010.
  2.	Chairman, International level conference titled "Springer sponsored Second International Conference on “Networks and Communications (NeCoM 2010)" from 23-Jul-2010 to 25-Jul-2010.
  1.	Chairman, International level conference titled "IEEE sponsored First International Conference on “Computational Intelligence and Communication Systems and Networks" from 23-Jul-2009 to 25-Jul-2009.

   

• Programme Organised

  8.	Coordinator, National level workshop on "workshop on "4G Wireless Technology" from 20-Feb-2014 to 21-Feb-2014. 9. coordinator, National level workshop on "UGC sponsored workshop on "Internet of Things"" from 01-Jan-2016 to 02-Jan-2016.
  7.	Coordinator, International level workshop on "Two days workshop on Recent Trends in Wireless Sensor Networks" from 28-Nov-2011 to 29-Nov-2011.
  6.	Coordinator, National level seminar on "National Seminar on Research challenges in wireless sensor networks" from 03-Mar-2010 to 03-Mar-2010.
  5.	Coordinator, National level workshop on "National workshop on “Next Generation Wireless Technology-Long Term Evolution (NGWT-LTE)" from 04-Dec-2009 to 05-Dec-2009.
  4.	Coordinator, International level workshop on "International workshop on Content based Image retrieval and fusion" from 07-Aug-2009 to 09-Aug-2009.
  3.	Coordinator, International level workshop on "Workshop on Recent trends in Wireless networks" from 26-Jul-2008 to 26-Jul-2008.
  2.	Coordinator, National level workshop on "Workshop on Next Generation Wireless Network" from 20-Sep-2007 to 22-Sep-2007.
  1.	Coordinator, National level workshop on "IEEE sponsored workshop on “Network Simulator for Wireless Networks" from 08-Sep-2007 to 09-Sep-2007.

• Programme Attended

   

  33.	Attended a National level Short Course on "AICTE Sponsored Staff Development Programme on “Robotics Technology for Manufacturing" , INDIA from 10-Dec-2011 to 23-Dec-2011.
  32.	Participated in a National level workshop on "Workshop on Simulation of Advanced Networks using NS-2 (WSAN’11)" organized by MIT ANNA UNIVERSITY, INDIA from 02-Dec-2011 to 03-Dec-2011.
  31.	Attended a National level Short Course on "MHRDE-AICTE Sponsored FDP on “Advances in Wireless Communication and Networking Technologies (AWCNT 2011)" organized by NIT Calicut, INDIA from 13-Jun-2011 to 24-Jun-2011.
  30.	Participated in a International level conference on "IEEE sponsored International Conference on “Recent Trends in Information Technology (ICRTIT 2011)" organized by MIT ANNA UNIVERSITY, INDIA from 03-Jun-2011 to 05-Jun-2011.
  29.	Participated in a International level workshop on "CPDE Sponsored Workshop on “Wireless Sensor Networks and Cloud Computing" organized by ANNA UNIVERSITY, INDIA from 16-May-2011 to 20-May-2011.
  28.	Attended a National level Short Course on "FDP on CS 2303 - Theory of Computation" organized by MIT ANNA UNIVERSITY, INDIA from 08-May-2011 to 12-May-2011.
  27.	Participated in a International level workshop on "International Workshop on Data Mining for Web Intelligence" organized by MIT ANNA UNIVERSITY, INDIA from 20-Jan-2011 to 21-Jan-2011.
  26.	Participated in a International level conference on "IEEE sponsored International Conference on “Computational Intelligence and Communication Networks (CICN 2010)" , INDIA from 26-Nov-2010 to 28-Nov-2010.
  25.	Participated in a International level workshop on "Wipro Sponsored Advanced Level Workshop" organized by MIT ANNA UNIVERSITY, INDIA from 15-Nov-2010 to 16-Nov-2010.
  24.	Participated in a International level conference on "Springer sponsored Second International Conference on “Networks and Communications (NeCoM 2010)" , INDIA from 23-Jul-2010 to 25-Jul-2010.
  23.	Attended a National level Short Course on "Wipro Sponsored Mission 10X – Faculty Empowerment Program" organized by MIT ANNA UNIVERSITY, INDIA from 21-Jun-2010 to 25-Jun-2010.
  22.	Participated in a National level workshop on "Wipro and ISTE Sponsored workshop on Mission 10X" organized by MIT ANNA UNIVERSITY, INDIA from 21-Jun-2010 to 22-Jun-2010.
  21.	Attended a National level seminar on "Agilent Technologies Sponsored one day seminar on “Understanding Digital and Cellular Standards and their measurements" organized by MIT ANNA UNIVERSITY, INDIA from 30-Apr-2010 to 30-Apr-2010.
  20.	Attended a National level seminar on "National Seminar on Research challenges in wireless sensor networks" organized by UGC SAP DRS, INDIA from 03-Mar-2010 to 03-Mar-2010.
  19.	Participated in a International level conference on "First International Conference on “Advanced Computing (ICAC 2009)" organized by MIT ANNA UNIVERSITY, INDIA from 13-Dec-2009 to 15-Dec-2009.
  18.	Participated in a International level workshop on "National workshop on “Next Generation Wireless Technology-Long Term Evolution (NGWT-LTE)" , INDIA from 04-Dec-2009 to 05-Dec-2009.
  17.	Participated in a International level workshop on "International workshop on Content based Image retrieval and fusion" organized by Centre for International Affairs Anna University, INDIA from 07-Aug-2009 to 09-Aug-2009.
  16.	Participated in a International level conference on "IEEE sponsored First International Conference on “Computational Intelligence and Communication Systems and Networks" , INDIA from 23-Jul-2009 to 25-Jul-2009.
  15.	Participated in a International level conference on "First National Conference on “Signal Processing Communications and VLSI Design (NCSCV’09)" organized by ANNA UNIVERSITY, INDIA from 08-May-2009 to 09-May-2009.
  14.	Participated in a International level workshop on "Two Days Workshop on “Pervasive and Ubiquitous Computing" organized by MIT ANNA UNIVERSITY, INDIA from 03-Apr-2009 to 04-Apr-2009.
  13.	Participated in a International level workshop on "IEEE sponsored One day workshop on Recent Trends in Wireless Networks" organized by MIT ANNA UNIVERSITY, INDIA from 26-Jul-2008 to 26-Jul-2008.
  12.	Participated in a International level conference on "Third International Conference on “Wireless Communication and Sensor Networks (WCSN 2007)" organized by IIT ALLAHABAD, INDIA from 13-Dec-2007 to 15-Dec-2007.
  11.	Participated in a International level conference on "IEEE sponsored International Conference on “Signal Processing, Communications and Networking (ICSCN 2007)" organized by MIT ANNA UNIVERSITY, INDIA from 22-Feb-2007 to 24-Feb-2007.
  10.	Participated in a National level workshop on "Workshop on “Electromagnetic Theory Revisited" organized by MIT ANNA UNIVERSITY, INDIA from 26-Jan-2007 to 27-Jan-2007.
  9.	Participated in a National level conference on "Second National Conference on Signals, Systems and Communications (NCSSC 2006)" organized by ANNA UNIVERSITY, INDIA from 01-Jun-2006 to 02-Jun-2006.
  8.	Attended a National level Short Course on "Continuing Education Programme on “Wireless Communication and Networks" organized by IIT KHARAGPUR, INDIA from 15-May-2006 to 20-May-2006.
  7.	Participated in a National level conference on "National Conference on CSIP – Emerging Trends in Computational Science and Information Processing" , INDIA from 01-Apr-2006 to 03-Apr-2006.
  6.	Participated in a National level workshop on "National Workshop on “Current Trends in Communication and Networking (CTCN 2006)" organized by MIT ANNA UNIVERSITY, INDIA from 24-Feb-2006 to 25-Feb-2006.
  5.	Attended a National level Short Course on "A Refresher Course on VLSI Design" organized by MIT ANNA UNIVERSITY, INDIA from 28-Mar-2005 to 29-Mar-2005.
  4.	Attended a National level Short Course on "Course organized by Centre for Faculty Development on “Principles of Environmental Science and Engineering" organized by MIT ANNA UNIVERSITY, INDIA from 06-Dec-2004 to 10-Dec-2004.
  3.	Participated in a International level workshop on "Two days Workshop on “DSP and Embedded Systems" organized by Sri Sai Ram Engineering College, INDIA from 06-Feb-2004 to 07-Feb-2004.
  2.	Participated in a National level conference on "IEEE Sponsored National Conference on Communication Networking NCCN 2003" organized by SRM Engineering College, INDIA from 26-Feb-2003 to 28-Feb-2003.
  1.	Attended a International level Short Course on "Beginner’s Course of Intel Teach to Future Program" organized by Intel, INDIA from 10-Oct-2002 to 24-Oct-2002.

   

• Supervisor Guidance (B.E/M.E)

   

  B.E Projects:

  Sl.No	Title	Year
  1.	Cell Range Expansion Technique In LTE Networks	2014
  2.	Activity Recognition And Classification Using Regression And Fuzzy Techniques	2014
  3.	Alcohol Detector	2014
  4.	Remote Access Of Home Appliances Using Humanoid Robot	2013
  5.	Foreign Object Debris Detection System For Aircraft Runways	2013
  6.	Humanoid Robot Based Physiotherapeutic Assistive Trainer For Elderly Health Care	2013
  7.	GSM Based Abnormality Detection System For Elderly Care	2013
  8.	Detection Of Cardiac Abnormalities In Bluetooth Based Body Sensor Network	2013
  9.	Ambulatory Monitoring Using Bluetooth Based Wearable Sensing Device	2013
  10.	Petri Net Based Workflow Automation Of Nephrology Unit Using Rfid	2012
  11.	Adaptive Traffic Signal Flow Control Using Wireless Sensor Networks	2012
  12.	An Efficient Mobility Based Localization In Underwater Wireless Sensor Networks	2012
  13.	Framework Development For Event Detection Application In WSN	2010
  14.	Person Detection And Tracking In Indoor WSN Environment	2010
  15.	Dasarathy Model based Fusion Framework for fire detection application in WSN	2010
  16.	Development of Fusion Framework with impression Compensated Event based Wireless Sensor Network	2010
  17.	Development Of Water Level Controller Using Wireless Sensor Networks	2009
  18.	Development Of Soil Moisture Monitoring System Using Wireless Sensor Networks	2009
  19.	RSSI And Trilateration Combined Indoor Localization Scheme For Wireless Sensor Networks	2009
  20.	Solar Energy  Harvesting for Wireless Sensor Networks	2008
  21.	Enhancement of DCF in 802.11	2007
  22.	SPEAR: Sensor Protocol for Energy Aware Routing	2007
  23.	LMR: Localized Multicast Routing for Wireless Sensor Networks	2006
  24.	Traffic Aware Time-out MAC protocol for Wireless Sensor Network	2006
  25.	Energy Efficient MAC protocol for Wireless Sensor Networks	2006

  M.E Projects: 

  Sl.No	Title	Year
  1.	Wavelet based OFDM implementation for LTE networks	2014
  2.	Comparative Study On Decision Tree Based Data Mining Algorithm To Assess Risk Of Epidemic	2013
  3.	Energy Efficient Cluster Based Routing In Wireless Sensor Network	2012
  4.	An Efficient Localized Voronoi Algorithm For Obstacle Detection In Wireless Sensor Networks	2011
  5.	Enhanced Call Admission Control For Wimax Networks	2010
  6.	An Efficient Localization Algorithm For Indoor Wireless Sensor Network	2009
  7.	Location Based Energy Efficient Routing In Wireless Sensor Networks	2009
  8.	Data Aggregation In Wireless Sensor Networks	2008
  9.	Modified WBIP Multicast Routing For Wireless Sensor Networks	2008
  10.	Energy Aware Multicast Routing In Wireless Sensor Networks	2008
  11.	Mathematical Modeling And Evaluation Of Spear Protocol	2007
  12.	Modeling And Performance Evaluation Of Wireless Sensor Networks	2007
  13.	Power Efficient And Delay Based Mac Protocol For Sensor Networks	2006
  14.	Localized Algorithm For Sensor Node Coverage, Connectivity And Its Traffic Analysis	2006
  15.	Localized Algorithm For Sensor Node Coverage And Its Connectivity In Wireless Sensor Network	2006
  16.	Energy Efficient and Secure MAC Protocol for Wireless Sensor Network	2006

   

   

• Research Oriented Training Undergone In India

   

  Advanced research training in Wireless Sensor Networks, Spann Lab, IIT, Bombay, 12-15 May 2008.

  Two-days Wireless Training on WLAN technology, Symbols Technologies India Pvt Ltd, Bangalore, 27th -28th June 2007.

   

• Lecture Notes

   

  P.T.V.Bhuvaneswari, V.Vaidehi and M.Agnes Saranya, “Distance Based Transmission Power Control scheme for Indoor Wireless Sensor Network”, Springer Journal (LNCS) Special Issue on Security in Computing of Transactions on Computational Sciences XI, Singapore, March, 2011, pp. 207-222 (Impact factor 0.084). 

   

• Experience Abroad

  1.	Visited WorldCOM, Nevada, USA from 11-Jul-2009 to 18-Jul-2009. Purpose of visit : Present Paper in International Conference.

• Contribution to outside world

   

  Sl. No	ACTIVITY	TENURE
  1.	Selection committee member for technical operator, Ayush, Government of INDIA	2012 -2013
  2.	TNPSC question paper setter	2012 till date
  3.	International Conferences review committee member	2011, 2012, 2013
  4.	Question Paper Scrutinizing committee member for Anna University affiliated colleges	2011, 2012, 2013
  5.	Springer and AIRCC International Journal reviewer	2012, 2013

   

• Research Guidance

   

  Scholars On-Roll
  S.No	Name of the Scholar	Reg.No	Ph.D./ M.S.	Full Time/ Part Time
  1	B. Panjavarnam	1423499708	Ph.D.	Part Time
  2	A.Saraswathi Priyadharshini	1423339749	Ph.D.	Full Time
  3	S.Ezhilarasi	1422439853	Ph.D.	Part Time
  4	K. Sri Dhivya Krishnan	1623339208	Ph.D.	Part Time
  5	V. Gokila Priya	1625438104	M. S.	Full Time

   

   

   

• Additional Responsibilties

   

  SL. No.	ACTIVITY	TENURE
  1.	Deputy Coordinator – UGC/DRS/SAP	2014-2019
  2.	Mentor – Industry Institute Partnership	2014
  3.	Placement committee member	2012
  4.	NRI Counselor	2013
  5.	Faculty Advisor	2004 – till date
  6.	NAAC Coordinator committee member for MIT	2014
  7.	NBA committee member	2014
  8.	U.G and P.G Project review committee member	2004 –till date
  9.	UGC purchase initiative (Qualnet, BWSIM)	2009 –2014
  10.	Technical committee member for Purchase in the Dept. of Information Technology, MIT	2011
  11.	Served as External Examiner for P.G Projects	2013
  12.	Formulated syllabus for Wireless Networks, Wireless Sensor Network and Wireless Mobile Communication	2012
  13.	Served as Additional Chief Superintendent for P.G (Communication and Networking)	2010-2011
  14.	Anna University Representative (AUR)	2009
  15.	Admission Duty of  U.G students	2011

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

Name                             :  Dr.D.Meganathan

Designation                     : Professor

Educational Qualification   : Ph.D

Area of Specialization        : VLSI

Email ID                          :  This email address is being protected from spambots. You need JavaScript enabled to view it.

IRINS Profile

• Educational qualifications

   

          

  Sl.No.	Examination Passed	Name of the University/Board	Year of Passing/ awarded	Subject/ Specialization
  1)	Post-Doc (By award)	KTH Royal Institute of Technology, Sweden	2011	VLSI/NOC Design
  2)	PhD	CEG, Anna University	2009	VLSI/Analog IC Design
  3)	ME	PSG tech, Bharathiar University	2003	Applied Electronics
  4)	AMIE	The Institution of Engineers (I)	1999	ELECTRICAL  AND ELECTRONICS ENGINEERING

• Post Held

   

  Post held	Period of Service		Name & Address of Employer
  	From	To
  Associate Professor	01-June-2015	Till Date	Anna University, Chennai
  Assistant Professor (Senior Scale)	10/07/2008	May-2015	Anna University, Chennai
  Lecturer	10/07/2003	09/07/2008	Anna University, Chennai
  Lecturer	10/03/2003	08/07/2003	Srikrishna Engineering College, Coimbatore

   

• Research Experience

   

  Post doctorate  in school of information and communication technology, 2010 – 2011 KTH Royal Institute of technology, Sweden.

   

  Title of the work: Concept and Design of Exhaustive-Parallel Search Algorithm to Support Quality-of-service in Network-on-Chip.

   

  Brief synopsis of Research: The work explores the concept and design of exhaustive-parallel search algorithm to support quality-of-service in Network-on-Chip. The exhaustive-parallel algorithm searches minimal path between source and destination in a wave-propagation manner. The algorithm is free from routing deadlock and live-lock. The algorithm guarantees setup latency if the setup path exists. A high performance switch is designed to support exhaustive-parallel search algorithm. The proposed router achieves the bandwidth of 1250Gb/s. The NoC fabric is designed for 8X8 mesh architecture and its performance is evaluated.

   

  Ph.D in faculty of information and communication Engineering, 2004-2009, College of Engineering, Anna University, India.

   

  Thesis Title: A Power Optimized 10-bit 100MS/s Pipelined Analog-to-Digital Converter for High Speed Interface Circuits.

   

  Brief synopsis of Research: High-speed and medium-resolution Analog-to-Digital Converters (ADC) are widely used in commercial applications including data communication and image signal processing. In such applications, the reduction of power consumption associated with high speed sampling and high linearity is one key design issue in enhancing the portability and battery operation. Among many ADC architectures, pipelined ADC is proved to be the most suitable for high-speed, medium-resolution and low-power consumption. Advancement in fabrication technology reduces the feature size of the transistor and scales down the supply voltage. To achieve high linearity, high dynamic range and high sampling speed simultaneously under low supply voltages in deep submicron Complementary Metal Oxide Semiconductor (CMOS) technology with low power consumption has been considered as extremely challenging. Thus, the objective of this work is to design and implement a low-voltage, low-power, medium-resolution and high-speed pipelined ADC in deep submicron CMOS technology.

   

  Masters in Department of Electrical and Electronics Engineering,2001-2003, PSG College of Engineering and Technology, India

   

  Project Title: Design and control of BLDC Motor using Microcontroller for Two Wheelers.

    

  Brief synopsis of project: The main objective of the project is to Design and develop a Brushless D.C Motor (BLDC) with control circuit for the operation of the hybrid electric vehicle (HEV) to be used in a two wheeler. The hybrid electric vehicle combines the power and the range of the conventional internal combustion (IC) vehicle with the zero-emission advantage of an electric vehicle creating an automotive solution for the polluted Indian roads. A HEV runs as a battery electric vehicle at the time of starting and runs up to 20 km per hour speed, beyond that it switch over to IC engine. The motor was fitted with the controller circuit in an existing two-wheeler and the performance was studied. The above project was carried out in M/s LUCAS-TVS, Chennai, India. 

• Work Experience

   

  2010 – 2011 Visiting Researcher, School of ICT , KTH Royal Institute of Technology, Sweden 

   

  I worked as a part of Professor Axel Jantsch research group in the field of network-on-chip. My research work involved in design and implementation of high performance interconnects to support quality of transmission in NoCs. I have developed a concept of exhaustive-parallel search algorithm which guarantees quality of transmission and setup latency. 

   

  2003 - till date Assistant Professor, Department of Electronics Engineering, Madras Institute of Technology, Anna University, India 

   

  I work as a regular faculty member in the department of electronics engineering. I have passion to teach electronics and VLSI related subjects. Besides teaching I have guided four numbers of post-graduate research projects and thirty numbers of undergraduate research projects. I worked as mentor for Texas-Instruments and IBM student projects. I have delivered several guest lectures on analog-integrated circuit design, VLSI Design, Electronic Circuits in various colleges/universities across India. 

   

• Fellowship

  EURINDIA Fellowship (2010-2011) to pursue post-doctorate research in KTH Royal Institute of technology, Sweden. 

• Journals

   

  1. D. Meganathan, S. Moorthi, Amrith Sukumaran, M. M. Dinesh Babu and J. Raja Paul Perinbam, “A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter”, Journal of Low Power Electronics Vol.4, 1–20, 2008.
  2. Moorthi S., Meganathan D., Janarthanan D., Praveen Kumar P. and Raja Paul Perinbam J., Low Jitter ADPLL based Clock Generator for High Speed SoC Applications’,         International Journal of  Electrical Computer and Systems Engineering, IJECSE Vol. 96, No. 11,  1183–1189,2009.
  3. D. Meganathan, A. Sukumaran, M.M.DineshBabu, S.Moorthi, Deepalakshmi R, “A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC” International Journal of  Microelectronics Journal Volume 40, Issue 10, pp.1417-1435, 2009.                                           
  4. D. Meganathan, Raja Paul Perinbam, R.Deepalakshmi, “High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC”, International Journal of High Performance Systems Architecture, Vol. 2, No. 1, 2009.
  5. D.Meganathan, “A 24.5mW, 10-bit, 50MS/sec CMOS pipelined Analog-to-Digital Converter” International Journal of High Performance Systems Architecture, Vol. 3, No. 4, pp-184-200, 2011.
  6. Jose Anand, J. Raja Paul Perinbam, and D. Meganathan, " Performance of Optimized Routing in Biomedical Wireless Sensor Networks using Evolutionary Algorithms", Comptes rendus ’Academie bulgare des Sciences, published by ENGINEERING SCIENCES. Vol. 68, Issue 8, pp. 1049-1054 (2015).
  7. Umamaheswari S , Meganathan D and Raja Paul Perinbam J, " Runtime Buffer ManagementTo Improve The Performance In Irregular Network-on-Chip Architecture", Journal of Systems Architecture, published by Sadhana, Indian Academy of Sciences, Springer. Vol. 10, Issue 4, pp. 1117-1137 (2015). 
  8. Jose Anand, J. Raja Paul Perinbam, and D. Meganathan, " Design of GA-Based Routing In Biomedical Wireless Sensor Networks", International Journal of Applied Engineering Research , Vol. 10, Issue 4, pp. 9281-9292 (2015).
  9. Jose Anand, J. Raja Paul Perinbam, and D. Meganathan, " PSO based Optimized Routing in Biomedical Wireless Sensor Networks", Jokull Journal, Vol. 65, Issue 3, pp. 9281-9292 (2015).
  10. D.R. Denslin Brabin, Raja Paul Perinbam, and D. Meganathan, " A High Capacity Data Hiding Scheme for Digital Images Using Normalization", International Journal of Applied Engineering Research, Vol. 10, Issue 1, pp. 1341-1350 (2015).
  11. Roy Francis, Meganathan D, "An Improved ANFIS with Aid of ALO Technique for THD Minimization of Multilevel Inverters", Journal of Circuits, Systems and Computers, , published by World Scientific. Vol. 27, Issue 12, (2018).
  12. Roy Francis, Meganathan D, " A Novel DDS Architecture for Dynamic Reconfigurable Three Phase Induction Motor Drive,", Journal of Electrical Engineering, published by University . Vol. 18, Issue 2, pp. 1-7 (2018).
  13. Madhusudhana Reddy Barusu, Umamaheswari Sethurajan, Meganathan Deivasigamani, " A non-invasive method for rotor bar fault diagnosis in three-phase squirrel cage induction motor with advanced signal processing technique", Journal of Engineering, published by IET. pp. 1-6 (2018).
  14. Madhusudhana Reddy Barusu, Umamaheswari Sethurajan, Meganathan Deivasigamani,"Low-cost SPLL-based electrical faults identification for three-phase squirrel cage induction motor using handheld Doppler radar signal analysisMadhusudhana Reddy Barusu", IET Power Electronics, published by IEEE. Vol. 11, Issue 7, pp. 1205-1216 (2018).
  15. Madhusudhana Reddy Barusu, Umamaheswari Sethurajan, Meganathan Deivasigamani, "Diagnosis of Bearing Outer Race Faults Using a low-cost non-contact method with Advanced Wavelet Transforms", Elektronika ir Elektrotechnika, published by ELEKTRONIKA IR ELEKTROTECHNIKA. Vol. 25, Issue 1, pp. 44-53 (2019).
  16. S.Balaji, D.Meganathan, "FPGA accelerated computing for particle identification in high-energy physics  experiments", IOP Press, published by IOP Press. pp. 1-6 (2019).
  17.  Roy Francis and D.Meganathan, "A dual-mode cascaded H-bridge multilevel inverter for improving THD", Journal of Electrical Engineering,, published by Springer. Vol. 101, Issue 1,pp. 225-236 (2019).
  18. S.Balaji, D.Meganathan and S.Ramasamy, "Single-Event-Hardened Timing Generator for waveform digitizer based readout electronics", Journal of Instrumentation , published by IOP Press. Vol. 14, pp. 1-8 (2019).
  19.  S.Jagannathanan, V. Sathiesh Kumara and D. Meganathan, " Design and Implementation of In-situ Human-Elephant Conflict Management", of Intelligent and Fuzzy Systems, , published by IOS Press. Vol. 36, Issue 3, pp. 2005-2013 (2019).
  20. D.R.Denslin Brabin, J.Rajapaul Perinbam, D.Meganathan, "Watermark visibility adjustable RVW scheme for JPEG images", Wireless Personal Communication, published by Springer.(2020).
  21.  K.Pandiammal, D.Meganathan, "Efficient design of QCA based hybrid multiplier using clockzone based crossover", Analog Integrated Circuits and Signal Processing, Vol. 102, pp. 63-77(2020). 
  22.  Madhusudhana Reddy Barusu, D. Meganathan, " Non-invasive Vibration Measurement for Diagnosis of Bearing Faults in 3-Phase Squirrel Cage Induction Motor Using Microwave Sensor", IEEE Sensors, published by IEEE. Vol. 21, Issue 2, pp. 1026-1039 (2021).
  23. Jagadeeshkumar N & Meganathan D, " A systematic design of novel energy efficient 64-bit parallel-prefix adder", International Journal of Electronics, published by Taylor and Francis. pp. 1-22 (2021).
  24. R. Denslin Brabin, J. Raja Paul Perinbam, D. Meganathan,, "A Block Based Reversible Data Hiding Scheme for Digital Images Using Optimal Value Computation", Wireless personal communication, published by Springer. Vol. 94, Issue 10, pp. 1-14 (2016).

  National Journal

  1. Jose Anand, J. Raja Paul Perinbam & D. Meganathan, "Q-Learning-Based Optimized Routing in Biomedical Wireless Sensor Networks", Networks’ IETE Journal of Research, published by Taylor and Francis . Vol. 63, Issue 1, pp. 89-97 (2017). 

• Conferences

  International Conferences

  1. Madhusudhana Reddy Barusu. Umamaheswari Sethurajan, Meganathan D, "A non-invasivemethod for rotor bar fault diagnosis in three-phase squirrel cage induction motor with advancedsignal processing technique" presented in a International level conference on The 9thInternational Conference on Power Electronics, Machines and Drives, organised by IET,Liverpool, UK from 17-Apr-2018 to 19-Apr-2018.
  2. Madhusudhana Reddy Barusu. Umamaheswari Sethurajan, Meganathan D, "Diagnosis ofBearing Outer Race Faults Using a low-cost non-contact method with Advanced WaveletTransforms" presented in a International level conference on ELECTRONICS -2018Conference, Lithuania, UK from 18-Jun-2018 to 20-Jun-2018.
  3. S.Jagannathan, V.Sathiesh Kumar and D.Meganahan, "Design and Implementation of In-situHuman-Elephant Conflict Management System" presented in a International level conferenceon Fourth International Symposium on Intelligent Systems Technologies and Applications ,organised by ISTA’18, India from 19-Sep-2018 to 22-Sep-2018.
  4. Pandiammal.K and D.Meganathan, "Design of 8 bit Reconfigurable ALU Using Quantum DotCellular Automata" presented in a International level conference on IEEE 13th Nanotechnology Materials and Devices Conference (NMDC), USA from 14-Oct-2018 to 17-Oct-2018.
  5. Jagadeesh Kumar N and Meganathan D, " A Novel Design of Low power and High speed Hybrid Multiplier " presented in a International level conferenceon 4th International Conference on Signal Processing, Communications and Networking,organised by Department of Electronics Engineering, MIT Campus, Anna University, India from16-Mar-2017 to 18-Mar-2017.
  6. Pandiammal K and Meganathan D, "QCA Based FIR Serial Multiplier using cut-set algorithm"presented in a International level conference on IEEE-Nano-2017, organised by Department ofElectrical and Computer Engineering, University of Pittsburgh, USA from 25-Jul-2017 to28-Jul-2017.
  7. S.Saranya, G.Sumithra, D.Meganathan, "An Approach to detect dolphin whistle from underwater sounds" presented in a International level conference on 3rd International Conference on Trends in Technology and Engineering, organised by ARJUN COLLEGE OF TECHNOLOGY, INDIA from 20-Apr-2016 to 20-Apr-2016.
  8. G.Sumithra, D.Meganathan, M.K.Suresh, "Noise Reduction in Underwater Acoustic Signals for Tropical and Subtropical Coastal Waters" presented in a International level conference on IEEE / OES, CHINA OCEAN ACOUSTICS SYMPOSIUM, COA 2016, organised by HARBIN ENGINEERING UNIVERSITY, CHINA &UNIVERSITÉ LIBRE DE BRUXELLES, BELGIUM, CHINA from 09-Jan-2016 to 11-Jan-2016.
  9. G.Sumithra,P.Yogapriya,D.Meganathan, "Shallow Water Path Model For Underwater Acoustic Communication" presented in a International level conference on 3rd International Conference and Exhibition on Underwater Acoustics, organised by FOUNDATION FOR RESEARCH &TECHNOLOGY HELLAS ; IACM – INSTITUTE OF APPLIED &COMPUTATIONAL MATHEMATICS , Greece from 21-Jun-2015 to 26-Jun-2015.
  10. Roy Francis, Meganathan. D, “Novel Static Reconfigurable PWM controller for Three Phase Induction motor drive”, Proceedings of the 8th International Conference on Science, Engineering and Technology (SET-2014),May 2014.
  11. Umamaheswari S , Meganathan D and Raja Paul Perinbam “Customized Adaptive Algorithm for Deadlock Free routing in irregular mesh NoC”, Proceedings of IET, 4th International Conference on Sustainable Energy and Intelligent system” Dec-12-14,2013.
  12. D.Meganathan, Shaghayeghsadat Tabatabaei, Axel Jantsch, Naveed Mustafa, Hamza Ijaz, Haris Bin Aslam, Shaoteng Liu, “Concept and Design of Exhaustive-Parallel search algorithm to support Quality-of-service in Network-on-Chip”, IEEE proceedings of SoCC-2011Conference,pp.150-155.
  13. D. Meganathan, Axel Jantsch, “A low-power, medium-resolution and high-speed CMOS pipelined ADC”, IEEE Proceedings of Norchip 2010 conference, pp-1-4.
  14. S.Moorthi, Meganathan D, J Raja Paul Perinbam,(2008) ‘A Low jitter ADPLL based clock generator circuit for High speed SoC applications’ in International conference on Computer Electrical and Systems Science and Engineering, Vol.33.

  National Conferences

  1. Meganathan D., Vishnu K.G., Hariharan and Raja Paul Perinbam J. (2007), ‘Macro-level Model of Pipelined ADC’, Proceedings of the International Conference on Modelling and Simulation, CITCOM 07,Coimbatore, India, Aug 27-29, Vol. 3, pp. 115-119. 
  2. Avijith singh, Meganathan D. and Raja Paul Perinbam J. (2008), ‘A Sub 1V low Power Voltage Reference Generator’, Proceedings of two day National Conference on Signals Systems and Communication, NCSSN’08, Chennai, India, May 8-9, pp. 184-187.
  3. K.Bhulakshmi, Meganathan D,(2008) ‘VLSI Implementation of Enhanced Encryption Techniques for public protocols’ Published in 4th National Conference on Signals, Systems and Communication.
  4. V. Ramana, Meganathan D.(2006) ‘Improving test effectiveness of SCAN based BIST by scan chain partitioning’ Published 2nd National Conference on Signals, Systems and Communication.

• Books authored

  1. D.Meganathan, “Hand-Book on Marine Electro technology for Marine Engineers” Chennai School of Ship Management, 2000.
  2. "Electronic Circuits-I" authored by D.Meganathan and published by Yesdee, Chennai.(2021)

• Programme Organised

   

  Sl.No.	Name of the Course	Duration	Venue
  1	Coordinator, National level workshop on "Advanced Digital Design Flow using CADENCE"	01-Mar-2018 to 03-Mar-2018	-
  2	Active member, International level conference on "4th International Conference on Signal Processing, Communications and Networking"	16-Mar-2017 to 17-Mar-2017.	-
  3	Workshop Coordinator, National level Short Course on "CMOS, Mixed Signal and Radio Frequency VLSI Design"	30-Jan-2017 to 04-Feb-2017.	-
  4	Coordinator, International level workshop on "UGC sponsored workshop on Embedded SoC Design"	07-Mar-2016 to 08-Mar-2016.	-
  5	Working Committee Member, International level conference on "3rd International conferenceon “Signal Processing, Communication and Networking (ICSCN 2015)"	26-Mar-2015 to28-Mar-2015.	-
  6	Two days workshop on Digital and Custom IC Design using CADENCE	Oct-17 & 18, 2014	Department of Electronics Engineering, MIT,AU
  7	Hands on training on VLSI System Design (RTL-GDSII) using CADENCE	Sep-22, 2014	Department of Electronics Engineering, MIT,AU
  8	Hands on training on Embedded System Design using ARM Controller	Sep-2,2014	Department of Electronics Engineering, MIT,AU
  9	One week Faculty development training program on VLSI Design	Dec 9-15,2013 (7-days)	Department of Electronics Engineering, MIT,AU
  10	Two-day Work-shop on Image processing frame work using FPGA”	Oct 15-16,2012 (2-days)	Department of Electronics Engineering, MIT,AU
  11	UGC Sponsored Two-day seminar on “Analog IC Design”	Sep 14-15,2012 (2-days)	Department of Electronics Engineering, MIT,AU
  12	Guest lecture on “Amplifier Design”	01-09-2009 (one-day)	Department of Electronics Engineering, MIT,AU
  13	Soft Skill Development Sponsored  by UGC for rural students	March-10 to 28, 2008	Department of Electronics Engineering, MIT,AU
  14	ASIC Design flow ( for Undergraduate and Post graduate students)	Sep 01-02, 2007 (02 days)	Department of Electronics Engineering, MIT,AU
  15	ARM Processor based development System (for Staffs and students)	May 23-24,2007 (02 days)	Department of Electronics Engineering, MIT,AU

   

• Invited Lectures Delivered

  Sl.No.	Topic of the lecture	Delivered on	Engineering College
  1	MOS Fabrication Techniques and CMOS Inverter	16-Nov-2018	Two week FDTP on VLSI Design-EC6601 organized by College of Engineering/Department of ECE, Chennai
  2	Hardwares in Networking"	16-Aug-2018	Guest Lecture organized by Valliammal  Engineering College/Department of Elect, Chennai
  3	Digital Circuit Design Digital Circuit Design" in Basic Concepts in Electronics andCommunication Lab Experiments	25-Jun-2018	Madras Institute of Technology/Department ofElect, Chenna
  4	CMOS Layout and Stick Diagrams	23-Nov-2017	Seven Days FDTP on VLSIDesign-EC6601 organized by Madras Institute of Technology/Center for Faculty , Chennai
  5	MOS Transistor Principles	20-Nov-2017	Seven Days FDTP on VLSIDesign-EC6601 organized by Madras Institute of Technology/Center for Faculty , Chennai.
  6	Electronic Circuits Design" in Basic Concepts in Electronics and Communication Lab Experiments	27-Jun-2017	Madras Institute of Technology/Department ofElect, Chennai .
  7	ADVANCED VLSI DESIGN TECHNIQUES	04-Aug-2016	VINAYAKA MISSIONS UNIVERSITY, Chennai .
  8	Challenges in Analog IC Design	14-Jul-2016	KCG College of Technology, Karapakkam, Chennai .
  9	Challenges in Analog IC design	19-Mar-2015	Conference organized by Anna University, Tirunelveli, Tirunelveli, Tamilnadu, India
  10	BJT Amplifiers	26th June 2014	Department of ECE, Dhanalakshmi College of Engineering, Tambaram, Chennai
  11	CMOS Inverter design	10th Dec 2013	Department of Electronics Engineering, MIT, AU.
  12	Analog VLSI Design	26th July 2013	Department of ECE, Anna University, Chennai-25.
  13	Challenges in Analog IC Design	14th Sep 2012	Department of Electronics Engineering, MIT Campus, Anna University,
  14	Guest lecture on Feedback Amplifiers	03/02/2010	VEL-Tech Multitech Engineering College Chennai
  15	Feedback Amplifiers	30.09.2009	RMK Engineering College, Chennai
  16	Introduction to Analog VLSI	01.09.2008	Vellore Institute of Technology University, Vellore.
  17	Analog Integrated circuit design	Dec 03-05, 2008	Lourdes Matha College of Science and Technology, Kerala

• Programme Attended

   

   

  Sl.No.	Title	Venue	Duration	Sponsoring Authority
  1	National level Short Course on "Personality Development and NLP".	National Institute of Technical Training & Research, India	20-Aug-2018 to 25-Aug-2018	National Institute of Technical Training & Research, India
  2	National level Short Course on "Professional Ethics and Values".	NITTTR, Chennai, India	27-Nov-2017 to 01-Dec-2017.	NITTTR, Chennai, India
  3	National level workshop on "High Frequency Design using ADS"	Department of Electronics Engineering, MIT Campus, Anna University, India	11-Aug-2017to 11-Aug-2017	Department of Electronics Engineering, MIT Campus, Anna University, India
  4	National level Short Course on "One Week ISTE STTP for Coordinators on CMOS,Mixed Signal and Radio Frequency VLSI Design"	IIT-Kharagpur, India	19-Sep-2016 to 23-Sep-2016	IIT-Kharagpur, India
  5	National level workshop on "Two Days workshop on Advancement in Biomedical Signal and Image Processing".	MIT Campus, India	29-Oct-2015to 30-Oct-2015	MIT Campus, India
  6	Participated in a International level workshop on "Hands-on Digital Signal Processing"	ARM University Program, , Hyderabad, India	20-Aug-2015 to 21-May-2015	ARM University Program, , Hyderabad, India
  7	Attended a National level Short Course on "FDP on Microprocessor and Microcontroller"	Madras Institute of Technology, Anna University, India	08-Jun-2015 to 14-Jun-2015	Madras Institute of Technology, Anna University, India
  8	One week Faculty development training program on VLSI Design	MIT Campus	Dec 9-15,2013 (7-days)	AICTE
  9	CMOS VLSI Design	NIT Calicut	23-29  June 2013 (7 days)	AICTE
  10	Robotics Technology for Manufacturing	MIT Campus	10/12/2011 to 23/12/2011 (14-days)	AICTE
  11	FDP on Digital Signal Processing	MIT Campus	28/11/2011 to 04/12/2011 (7 days)	Centre for FDP,Anna University
  12	Advances in wireless Communication and networking Technologies	NIT-Calicut	13/06/2011 to 24/06/2011 (12 days)	MHRDE-AICTE
  13	Course on “Floorplanning, Physical synthesis, Place and Route (Flat and Hierarchical)+Low power implementation”	KTH-Royal Institute of Technology, Sweden.	20/09/2010 to 28/09/2010 (10 days)	KTH-Royal Institute of Technology
  14	One day workshop on Pattern recognition	MIT Campus	19/03/10 (one day)	MIT Campus
  15	TI Developer Conference	Leela Palace, Bangalore	29/07/2007 to 30/07/2007 (2 days)	Texas Instrument
  16	Two Weeks Course on Analog Design	TCE, Madurai	04/06/2007 to 15/06/2007 (12 days)	Texas Instrument
  17	One day workshop on Engineering trends in VLSI and ASIC design	CEG, Anna University	07/04/07 (one day)	Anna University
  18	Embedded Systems and Technology	IIT Kharagpur	19/06/2006 to 24/06/2006 (6 days)	TEQIP.
  19	Digital Signal Processing	CEG, Anna University	13/06/05 to 18/06/05 (6 days)	CEG, Anna University.
  20	VLSI and Embedded system Tool	CEG, Anna University	25/01/05 (one day)	CEG, Anna University.
  21	VLSI Design	CEG, Anna University	21/06/2004 to 27/06/2004 (7 days)	CEG, Anna University
  22	RE-Engineering teaching skills	MIT, Anna University	06/04/2004 to 07/04/2004 (2 days)	MIT, Anna University
  23	Digital Signal Processing	CEG,Anna University	18/11/2003 to 22/11/2003 (5 days)	CEG,Anna University
  24	Three days training program on “Modern teaching Competencies for faculty members	Sri Krishna College of Engineering and Technology	21/03/2003 to 23/03/2003 (3 days)	Sri Krishna College of Engineering and Technology

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

   

• Purchase Activity

   

   

   

  Sl.No.	Hardware/ Equipment purchase	Amount Approximately
  1)	MATLAB-Full Suite	Rs.15,00,000/-
  2)	Digital Storage Oscilloscope	Rs.4,00,000/-
  3)	Mixed Signal Oscilloscope	Rs.6,02,000/-
  4)	Function Generator	Rs.3,00,000/-
  5)	Red-had Linux Software for CADENCE platform	Rs.25,000/-
  5)	Rivera IPT	Rs.12,00,000/-
  6)	ARM Processor based Development Systems (Embedded Systems)	Rs.12,00,000/-
  7)	Logic Analyzer	Rs. 4,50,000/-
  8)	RFID, Sensor networks and Digital Storage Oscilloscope	Rs. 2,50,000/-
  9)	CADENCE Full Suite	Rs.14,00,000
  10)	Mixed Signal Oscilloscope (5)	Rs.9,00,000
  11)	Arbitrary Function Generator 40 MHz (5)	Rs.6,00,000
  12)	Digital Multimeter-5.5 digit (2)	Rs.1,00,000
  13)	Variable Power Supply (20)	Rs.5,00,000
  14)	3-MHz Function Generator (30)	Rs.3,00,000

   

• Student Activities

   

  i)                    President-EEA 

  I have been nominated as President, Electronic Engineer Association (EEA) in the Department of Electronics Engineering, MIT, AU for the academic year of 2013-14. EEA conducts various technical events like apocalypse, Electro focus etc., Besides our regular EEA activities, EEA organized several workshops, arranged GATE coaching and placement training for the students of the Department of Electronics Engineering, MIT Campus, Anna University during 2013-14. EEA awarded 10-scholarships for economically weaker students.

   

  ii)                  Coordinator- IETE Student Chapter  

  Organized invited lectures by eminent personalities from industries and academics. This chapter had largest strength among IETE student chapter of Tamilnadu.

   

  Sl.No.	Topic of the lecture	Delivered on	Expert Name and Address
  1)	Recent trends in Broad band Technologies	26.10.2006	Mr.A.Ganesan, Divisional General Manager, BSNL Chennai Circle- Chennai
  2)	Short term course on ASIC Design Flow	September 01-02,2007	1) Dr. J.Raja Paul Perinbam, Professor Anna University 2) Mr.S.Moorthi, Lecturer, NIT Trichy 3) Mr. A. Ganesan, Divisional General Manager, BSNL Chennai Circle- Chennai.

• Funded Projects

   

   

  S.No	Sponsored/ Consultancy Projects	Sponsoring Authority	Funds Sanctioned	Present Status
  1)	Design and Analysis of Phase locked loop based high speed clock generation for system on-chip applications	TEQIP-Networking	Rs.2Lacs	Completed
  2)	A Proposal for Low cost human-elephant conflict management in wildlife	Aeronautical Research & Development Board (Sigma Panel)	Rs 19,61,900 /-	Completed

   

   

• Ph.D Guidance(at present)

   

  Ph.D Completed
  Name of the PhD Scholar	Mode	Title of the Research work
  Mrs.S. Uma Maheswari	Part-time (Internal)	Performance Enhancement in NoC applications
  Mr.Roy Francis	Part-time (QIP)	Dynamic Reconfigurable Multilevel Inverter
  Mr. .Madhusudhana Reddy Barusu	Part-time (External)	Mutually Synchronized Oscillator’s Network for Clock Distribution on Large-Scale SOCs
  Ph.D On-Roll
  Name of the PhD Scholar	Mode	Title of the Research work
  Mr. N.Jagadeesh Kumar	Part-time (Internal)	Digital Logic Design using CNTFET
  Ms.K.Pandiammal	Part-time  (External)	Digital logic Design using Quantum-Cellular-Automata
  Ms. G. Sumithra	Part-time (Internal)	Under water Acoustic Communication

   *Welcoming young enthusiastic, dynamic minded people who want to pursue PhD

• Reviewer

   

  Reviewer for Elsevier Microelectronics Journal 

• Prizes,Awards Received

   

  (i) I have received prize award from the Institution of Engineers (I) for securing highest marks in aggregate amongst the successful candidates  in AMIE (Sec-B) Winter 1999 Exams.

  (ii) I have received IBM University relationship award for mentoring UG students,2011

   

• Subjects Handled

  UG Program

  1)      Electronic Circuits I

  2)      Electronic Circuits II

  3)      Digital System Design

  4)      Digital VLSI

  5)      Analog IC Design

  6)      Circuit Analysis

  7)      VLSI Design

  8)      Electron Devices

  9)      Electromagnetic Field theory

  10)  Network Analysis and Synthesis

  11)  Neural Networks and Fuzzy Logic Design

  PG Program

  1)      VLSI Design Techniques

  2)       ASIC Design

  Analog IC Design

• Additional Responsibilities

   

  1. Serving as Faculty Advisor since-2003.
  2. Guiding PG/UG Projects.
  3. Served as NRI Coordinator.
  4. Served as Part-time Coordinator.
  5. Handled Part-time classes continuously from 2003-2012.
  6. Actively involved in the syllabus framing work (2004,2008 & 2012).
  7. Developed Full-Fledged Analog VLSI Lab in the Department of Electronics Engineering, MIT Campus, Anna University.
  8. Served as Project Coordinator for PhD/PG/UG students.
  9. Guided Several PG and UG Projects.
  10. Working team member for International Conference on Signals, Communication and Networking Conferences -2007 and 2008.
  11. Executive Warden, Madras Institute of Technology, Anna University, Chennai from September-2019.
  12. Class Committee Chairman-(ME VLSI Design and Embed, Department of Electronics Engineering, Anna University, Chennai from June-2018.
  13. Class Committee Chairman -(be-i Year), Department of Electronics Engineering, Anna University, Chennai during December-2017 and May-2018.
  14. Faculty Advisor, Department of Electronics Engineering, Anna University, Chennai during August-2015 and July-2016.
  15. Class Committee Chairman (me-vlsi Design And Embed, Department of Electronics Engineering, Anna University, Chennai during July-2015 and December-2017.
  16. Deputy Warden, , Anna University, Chennai during August-2014 and September-2019.
  17. President Electronics Engineers Association, Department of Electronics Engineering, Anna University, Chennai during August-2013 and April-2014.
  18. Faculty Advisor, Department of Electronics Engineering, Anna University, Chennai during August-2011 and April-2015.
  19. Facutly Advisor, Department of Electronics Engineering, Anna University, Chennai during August-2007 and April-2010.
  20. Additional Chief Superintendent For End Semester E, MIT, Anna University, Chennai during Novem ber-2005 and January-2006.
  21. Additional Course Coordinator, Department of Electronics Engineering, Anna University, Chennai during August-2003 and April-2008.
  22. Faculty Advisor, Department of Electronics Engineering, Anna University, Chennai during July-2003 and April-2007.